Rainbow Electronics DS3170 - Manual (Page 166)

DS3170 DS3/E3 Single-Chip Transceiver
166 of 233
Register Name: FEAC.RSR
Register Description: FEAC Receive Status Register
Register Address: 0D4h
Bit
# 15 14 13 12 11 10 9 8
Name -- -- -- -- -- -- -- --
Bit
# 7 6 5 4 3 2 1 0
Name -- -- -- -- RFFE -- RFCD RFI
Bit 3: Receive FEAC FIFO Empty (RFFE) – When 0, the Receive FIFO contains at least one code. When 1, the
Receive FIFO is empty.
Bit 1: Receive FEAC Codeword Detect (RFCD) – When 0, the Receive FEAC Processor is not currently receiving
a FEAC codeword. When 1, the Receive FEAC Processor is currently receiving a FEAC codeword.
Bit 0: Receive FEAC Idle (RFI) – When 0, the Receive FEAC processor is not receiving a FEAC Idle signal (all
ones). When 1, the Receive FEAC processor is receiving a FEAC Idle signal.
Register Name:
FEAC.RSRL
Register Description: FEAC Receive Status Register Latched
Register Address: 0D6h
Bit
# 15 14 13 12 11 10 9 8
Name -- -- -- -- -- -- -- --
Bit
# 7 6 5 4 3 2 1 0
Name -- -- -- -- -- RFFOL RFCDL RFIL
Bit 2: Receive FEAC FIFO Overflow Latched (RFFOL) – This bit is set when a Receive FIFO overflow condition
occurs. An overflow condition results in a loss of data.
Bit 1: Receive FEAC Codeword Detect Latched (RFCDL) – This bit is set when the RFCD bit transitions from 0
to 1.
Bit 0: Receive FEAC Idle Latched (RFIL) – This bit is set when the RFI bit transitions from 0 to 1. Note:
Immediately after a reset, this bit will be set to one.
Register Name:
FEAC.RSRIE
Register Description: FEAC Receive Status Register Interrupt Enable
Register Address: 0D8h
Bit
# 15 14 13 12 11 10 9 8
Name -- -- -- -- -- -- -- --
Default 0 0 0 0 0 0 0 0
Bit
# 7 6 5 4 3 2 1 0
Name -- -- -- -- -- RFFOIE RFCDIE RFIIE
Default 0 0 0 0 0 0 0 0
Bit 2: Receive FEAC FIFO Overflow Interrupt Enable (RFFOIE) – This bit enables an interrupt if the RFFOL bit
is set and the bit in
GL.ISRIE .PSRIE[4:1] that corresponds to this port is set.
0 = interrupt disabled
1 = interrupt enabled