Rainbow Electronics DS3170 - Manual (Page 127)

DS3170 DS3/E3 Single-Chip Transceiver
127 of 233
Register Name: GL.CR1
Register Description: Global Control Register 1
Register Address: 002h
Bit
# 15 14 13 12 11 10 9 8
Name -- INTM -- -- -- -- -- --
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Name TMEI MEIMS GPM1 GPM0 PMU LSBCRE RSTDP RST
Default 0 0 0 0 0 0 1 0
Bit 14: INT pin mode (INTM) This bit determines the inactive mode of the INT pin. The INT pin always drives low
when active.
0 = Pin is high impedance when not active
1 = Pin drives high when not active
Bit 7: Transmit Manual Error Insert (TMEI) This bit is used insert an error if the port is configured for global error
insertion. An error(s) is inserted at the next opportunity when this bit transitions from low to high. The
GL.CR1 .MEIMS bit must be clear for this bit to operate.
Bit 6: Transmit Manual Error Insert Select (MEIMS) This bit is used to select the source of the global manual
error insertion signal
0 = Global error insertion using TMEI bit
1 = Global error insertion using the GPIO6 pin
Bits 5 and 4: Global Performance Monitor Update Mode (GPM[1:0]) These bits select the global performance
monitor register update mode.
00 = Global PM update using the PMU bit
01 = Global PM update using the GPIO8 pin
1x = One second PM update using the internal one second counter
Bit 3: Global Performance Monitor Update Register (PMU) This bit is used to update all of the performance
monitor registers configured to use this bit. When this bit is toggled from low to high the performance registers
configured to use this signal will be updated with the latest count value from the counters, and the counters will be
reset. The bit should remain high until the performance register update status bit (
GL.SR .PMS) goes high, then it
should be brought back low which clears the PMS status bit.
Bit 2: Latched Status Bit Clear on Read Enable (LSBCRE). This signal determines when latched status register
bits are cleared.
0 = Latched status register bits are cleared on a write
1 = Latched status register bits are cleared on a read
Bit 1: Reset Data Path (RSTDP). When this bit is set, it will force all of the internal data path registers to their
default state. This bit must be set high for a minimum of 100ns. See the
Reset and Power-Down section 9.3 . Note:
The default state is a 1 (after a general reset, this bit will be set to one).
0 = Normal operation
1 = Force all data path registers to their default values
Bit 0: Reset (RST). When this bit is set, all of the internal data path and status and control registers (except this
RST bit), will be reset to their default state. This bit must be set high for a minimum of 100ns. See the
Reset and
Power-Down section 9.3 .
0 = Normal operation
1 = Force all internal registers to their default values