Rainbow Electronics DS3170 - Manual (Page 169)

DS3170 DS3/E3 Single-Chip Transceiver
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Register Name:
TT.TTIAR
Register Description: Trail Trace Transmit Identifier Address Register
Register Address: 0EAh
Bit
# 15 14 13 12 11 10 9 8
Name -- -- -- -- -- -- -- --
Default 0 0 0 0 0 0 0 0
Bit
# 7 6 5 4 3 2 1 0
Name -- -- Reserved Reserved TTIA3 TTIA2 TTIA1 TTIA0
Default 0 0 0 0 0 0 0 0
Bits 3 to 0: Transmit Trail Trace Identifier Address (TTIA[3:0]) – These four bits indicate the transmit trail trace
identifier byte to be read/written by the next memory access. Address 0h indicates the first byte of the transmit trail
trace identifier. Note: The value of these bits increments with each transmit trail trace identifier memory access
(when these bits are Fh, a memory access will return them to 0h).
Register Name:
TT.TIR
Register Description: Trail Trace Transmit Identifier Register
Register Address: 0ECh
Bit
# 15 14 13 12 11 10 9 8
Name -- -- -- -- -- -- -- --
Default 0 0 0 0 0 0 0 0
Bit
# 7 6 5 4 3 2 1 0
Name TTD7 TTD6 TTD5 TTD4 TTD3 TTD2 TTD1 TTD0
Default
0 0 0 0 0 0 0 0
Bits 7 to 0: Transmit Trail Trace Identifier Data (TTD[7:0]) – These eight bits are the transmit trail trace identifier
data. The transmit trail trace identifier address will be incremented whenever these bits are read or written (when
address location Fh is read or written, the address will return to 0h).
11.8.2 Trail Trace Receive Side Register Map
The receive side utilizes seven registers.
Table 11-21. Trail Trace Receive Side Register Map
Address Register
Register Description
0F0h TT.RCR Trail Trace Receive Control Register
0F2h TT.RTIAR Trail Trace Receive Identifier Address Register
0F4h TT.RSR Trail Trace Receive Status Register
0F6h TT.RSRL Trail Trace Receive Status Register Latched
0F8h TT.RSRIE Trail Trace Receive Status Register Interrupt Enable
0FAh -- Unused
0FCh TT.RIR Trail Trace Receive Identifier Register
0FEh TT.EIR Trail Trace Expected Identifier Register