Rainbow Electronics DS3170 - Manual (Page 27)

DS3170 DS3/E3 Single-Chip Transceiver
27 of 233
PIN
NAME TYPE FUNCTION
BGA LQFP
AVSSR PWR Analog Gnd for Receive LIU B5 92
AVSST PWR Analog Gnd for Transmit LIU E4 14
AVSSJ PWR Analog Gnd for Jitter Attenuator D2 10
AVSSC PWR Analog Gnd for CLAD G1 19
UNUSED
UNUSED1 N/A Unused D6 89
UNUSED2 N/A Unused G2 20
7.2 Detailed Pin Descriptions
Table 7-2. Detailed Pin Descriptions
Ipu (input with pullup), Oz (output tri-stateable), Oa (Analog output), Ia (analog input), IO (Bidirectional inout)
PIN NAME TYPE PIN DESCRIPTION
Line IO
TLCLK O Transmit Line Clock Output
TLCLK: This signal is available when the transmit line interface pins are enabled
(
PORT.CR2. TLEN). This clock is typically used as the clock reference for the TDAT
and TNEG signals, but can also be used as the reference for the TSOFI, TSER, and
TSOFO / TDEN signals.
This output signal can be inverted.
o DS3: 44.736 MHz +20 ppm
o E3: 34.368 MHz +20 ppm
TPOS /
TDAT O Transmit Positive AMI / Data Output
TPOS: When the port line interface is configured for B3ZS, HDB3 or AMI mode and
the transmit line interface pins are enabled (
PORT.CR2. TLEN), a high on this pin
indicates that a positive pulse should be transmitted on the line. The signal is updated
on the positive clock edge of the referenced clock pin if the clock pin signal is not
inverted, otherwise it is updated on the falling edge of the clock. The signal is typically
referenced to the TLCLK line clock output pins, but it can be referenced to the
TCLKO, TCLKI, RLCLK or RCLKO pins. This output signal can be disabled when the
TX LIU is enabled.
This output signal can be inverted.
TDAT: When the port line interface is configured for UNI mode and the transmit line
interface pins are enabled (
PORT.CR2. TLEN), the un-encoded transmit signal is
output on this pin. The signal is updated on the positive clock edge of the referenced
clock pin if the clock pin signal is not inverted, otherwise it is updated on the falling
edge of the clock. The signal is typically referenced to the TLCLK line clock output
pins, but it can be referenced to the TCLKO, TCLKI, RLCLK or RCLKO pins
This output signal can be inverted.
o DS3: 44.736 Mbps +20ppm
o E3: 34.368 Mbps +20ppm