Rainbow Electronics DS3170 User Manual
General description, Applications, Ordering information
1 of 233
REV: 101404
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, clic
GENERAL DESCRIPTION
The DS3170 combines a DS3/E3 framer and an LIU
(single-chip transceiver) to interface to a DS3/E3
physical copper line.
APPLICATIONS
Access Concentrators
Routers and Switches
Multiservice Access
Platforms (MSAPs)
SONET/SDH ADM
SONET/SDH Muxes
Multiservice Protocol
Platform (MSPPs)
PBXs Test
Equipment
Digital Cross Connect
PDH Multiplexer/
Demultiplexer
Integrated-Access Device
(IAD)
ORDERING INFORMATION
PART TEMP
RANGE
PIN-PACKAGE
DS3170
0°C to +70°C
100 CSBGA (11mm x
11mm, 1mm pitch)
DS3170L
0°C to +70°C
100 LQFP (14mm x
14mm, 1.4mm pitch)
DS3170N
-40°C to +85°C
100 CSBGA (11mm x
11mm, 1mm pitch)
DS3170LN
-40°C to +85°C
100 LQFP (14mm x
14mm, 1.4mm pitch)
FUNCTIONAL DIAGRAM
DS3170
DS3/E3 LINE
DS3/
E3
LIU
DS3/E3
FRAMER/
FORMATTER
SYSTEM
BACKPLANE
FEATURES
§ Single-Chip Transceiver for DS3 and E3
§ Performs Receive Clock/Data Recovery and
Transmit Waveshaping for DS3 and E3
§ Jitter Attenuator can be Placed Either in the
Receive or Transmit Path
§ Interfaces to 75W Coaxial Cable at Lengths Up to
380 Meters or 1246 Feet (DS3), or 440 Meters or
1443 Feet (E3)
§ Uses 1:2 Transformers on Both Tx and Rx
§ On-Chip DS3 (M23 or C-Bit) and E3 (G.751 or
G.832) Framer
§ Built-In HDLC Controller with 256-Byte FIFO for
the Insertion/Extraction of DS3 PMDL, G.751 Sn
Bit, and G.832 NR/GC Bytes
§ On-Chip BERT for PRBS and Repetitive Pattern
Generation, Detection and Analysis
§ Large Performance-Monitoring Counters for
Accumulation Intervals of At Least 1 Second
§ Flexible Overhead Insertion/Extraction Port for
DS3, E3 Framers
§ Loopbacks Include Line, Diagnostic, Framer,
Payload, and Analog with Capabilities to Insert
AIS in the Directions Away from Loopback
Directions
§ Integrated Clock Rate Adapter to Generate the
Remaining Internally Required 44.736MHz (DS3)
and 34.368MHz (E3) from a Single-Clock
Reference Source
§ CLAD Reference Clock can be 44.736MHz,
34.368MHz, 77.76MHz, 51.84MHz, or 19.44MHz
§ Software Compatible with DS3171–DS3174 SCT
Product Family
§ 8-/16-Bit Parallel and Slave SPI Serial (≤10Mbps)
Microprocessor Interface
§ Low-Power (0.5W) 3.3V Operation (5V Tolerant
I/O)
§ 100-Pin Small 11mm (1mm) CSBGA and 14mm
(1.4mm) LQFP Package Options
§ Industrial Temperature Operation: -40°C to +85°C
§ IEEE1149.1 JTAG Test Port
PRODUCT BRIEF
DS3170
DS3/E3 Single-Chip Transceiver
www.maxim-ic.com
Document Outline
- BLOCK DIAGRAMS
- APPLICATIONS
- FEATURE DETAILS
- Global Features
- Receive DS3/E3 LIU Features
- Jitter Attenuator Features
- Receive DS3/E3 Framer Features
- Transmit DS3/E3 Formatter Features
- Transmit DS3/E3 LIU Features
- Clock Rate Adapter Features
- HDLC Controller Features
- FEAC Controller Features
- Trail Trace Buffer Features
- Bit Error-Rate Tester (BERT) Features
- Loopback Features
- Microprocessor Interface Features
- Slave Serial Peripheral Interface (SPI) Features
- Test Features
- STANDARDS COMPLIANCE
- ACRONYMS AND GLOSSARY
- MAJOR OPERATIONAL MODES
- PIN DESCRIPTIONS
- INITIALIZATION AND CONFIGURATION
- FUNCTIONAL DESCRIPTION
- Processor Bus Interface
- Clocks
- Reset and Power-Down
- Global Resources
- Port Resources
- DS3/E3 Framer / Formatter
- General Description
- Features
- Transmit Formatter
- Receive Framer
- C-bit DS3 Framer/Formatter
- M23 DS3 Framer/Formatter
- G.751 E3 Framer/Formatter
- G.832 E3 Framer/Formatter
- Transmit G.832 E3 Frame Processor
- Transmit G.832 E3 Frame Generation
- Transmit G.832 E3 Error Insertion
- Transmit G.832 E3 Overhead Insertion
- Transmit G.832 E3 AIS Generation
- Receive G.832 E3 Frame Processor
- Receive G.832 E3 Framing
- Receive G.832 E3 Performance Monitoring
- Receive G.832 E3 Overhead Extraction
- Receive G.832 Downstream AIS Generation
- HDLC Overhead Controller
- Trail Trace Controller
- FEAC Controller
- Line Encoder/Decoder
- BERT
- LIU – Line Interface Unit
- OVERALL REGISTER MAP
- REGISTER MAPS AND DESCRIPTIONS
- JTAG INFORMATION
- PIN CONFIGURATIONS
- PACKAGE INFORMATION
- PACKAGE THERMAL INFORMATION
- DC ELECTRICAL CHARACTERISTICS
- AC TIMING CHARACTERISTICS
- REVISION HISTORY