Rainbow Electronics DS3170 - Manual (Page 194)

DS3170 DS3/E3 Single-Chip Transceiver
194 of 233
11.9.6 Receive G.832 E3 Register Map
The receive G.832 E3 utilizes thirteen registers.
Table 11-27. Receive G.832 E3 Framer Register Map
Address
Register
Register Description
120h E3G832.RCR E3 G.832 Receive Control Register
122h E3G832.RMACR E3 G.832 Receive MA Byte Control Register
124h E3G832.RSR1 E3 G.832 Receive Status Register #1
126h E3G832.RSR2 E3 G.832 Receive Status Register #2
128h E3G832.RSRL1 E3 G.832 Receive Status Register Latched #1
12Ah E3G832.RSRL2 E3 G.832 Receive Status Register Latched #2
12Ch E3G832.RSRIE1 E3 G.832 Receive Status Register Interrupt Enable #1
12Eh E3G832.RSRIE2 E3 G.832 Receive Status Register Interrupt Enable #2
130h E3G832.RMABR E3 G.832 Receive MA Byte Register
132h E3G832.RNGBR E3 G.832 Receive NR and GC Byte Register
134h E3G832.RFECR E3 G.832 Receive Framing Error Count Register
136h E3G832.RPECR E3 G.832 Receive Parity Error Count Register
138h E3G832.RFBER E3 G.832 Receive Remote Error Indication Count Register
13Ah -- Reserved
13Ch -- Unused
13Eh -- Unused
11.9.6.1 Register Bit Descriptions
Register Name:
E3G832.RCR
Register Description: E3 G.832 Receive Control Register
Register Address: 120h
Bit
# 15 14 13 12 11 10 9 8
Name Reserved PEC DLS MDAISI AAISD ECC FECC1 FECC0
Default 0 0 0 0 0 0 0 0
Bit
# 7 6 5 4 3 2 1 0
Name RAILE RAILD RAIOD RAIAD ROMD LIP1 LIP0 FRSYNC
Default
0 0 0 0 0 0 0 0
Bit 14: Parity Error Count (PEC) – When 0, BIP-8 block errors (EM byte) are detected (no more than one per
frame). When 1, BIP-8-bit errors are detected (up to 8 per frame).
Bit 13: Receive HDLC Data Link Source (DLS) – When 0, the receive HDLC data link will be sourced from the
GC byte. When 1, the receive HDLC data link will be sourced from the NR byte.
Bit 12: Manual Downstream AIS Insertion (MDAISI) – When 0, manual downstream AIS insertion is disabled.
When 1, manual downstream AIS insertion is enabled.
Bit 11: Automatic Downstream AIS Disable (AAISD) – When 0, the presence of an LOS, OOF, or AIS condition
will cause downstream AIS to be inserted. When 1, the presence of an LOS, OOF, or AIS condition will not cause
downstream AIS to be inserted.
Bit 10: Error Count Control (ECC) – When 0, framing errors, parity errors, and REI errors will not be counted if an
OOF or AIS condition is present. Parity errors and REI errors will also not be counted during the E3 frame in which
an OOF or AIS condition is terminated, and the next E3 frame. When 1, framing errors, parity errors, and REI
errors will be counted regardless of the presence of an OOF or AIS condition.