Rainbow Electronics DS3170 - Manual (Page 160)

DS3170 DS3/E3 Single-Chip Transceiver
160 of 233
Bit 0: Receive FIFO Reset (RFRST) – When 0, the Receive FIFO will resume normal operations, however, data is
discarded until a start of packet is received after RAM power-up is completed. When 1, the Receive FIFO is
emptied, any transfer in progress is halted, the FIFO RAM is powered down, the RHDA bit is forced low, and all
incoming data is discarded.
Register Name:
HDLC.RSR
Register Description: HDLC Receive Status Register
Register Address: 0B4h
Bit
# 15 14 13 12 11 10 9 8
Name -- -- -- -- -- -- -- --
Bit
# 7 6 5 4 3 2 1 0
Name -- -- -- -- -- RFF RFE RHDA
Bit 2: Receive FIFO Full (RFF) – When 0, the Receive FIFO contains 255 or less bytes of data. When 1, the
Receive FIFO is full.
Bit 1: Receive FIFO Empty (RFE) – When 0, the Receive FIFO contains at least one byte of data. When 1, the
Receive FIFO is empty.
Bit 0: Receive HDLC Data Available (RHDA) – When 0, the Receive FIFO contains less data than the Receive
HDLC data available level (RDAL[4:0]). When 1, the Receive FIFO contains the same or more data than the
Receive HDLC data available level.
Register Name:
HDLC.RSRL
Register Description: HDLC Receive Status Register Latched
Register Address: 0B6h
Bit
# 15 14 13 12 11 10 9 8
Name -- -- -- -- -- -- -- --
Bit
# 7 6 5 4 3 2 1 0
Name RFOL -- -- RPEL RPSL RFFL -- RHDAL
Bit 7: Receive FIFO Overflow Latched (RFOL) – This bit is set when a Receive FIFO overflow condition occurs.
An overflow condition results in a loss of data.
Bit 4: Receive Packet End Latched (RPEL) – This bit is set when an end of packet is stored in the Receive FIFO.
Bit 3: Receive Packet Start Latched (RPSL) – This bit is set when a start of packet is stored in the Receive FIFO.
Bit 2: Receive FIFO Full Latched (RFFL) – This bit is set when the RFF bit transitions from 0 to 1.
Bit 0: Receive HDLC Data Available Latched (RHDAL) – This bit is set when the RHDA bit transitions from 0 to
1.