Feac.rfdr – Rainbow Electronics DS3170 User Manual
Page 167
DS3170 DS3/E3 Single-Chip Transceiver
167 of 233
Bit 1: Receive FEAC Codeword Detect Interrupt Enable (RFCDIE) – This bit enables an interrupt if the RFCDL
bit is set and the bit in
.PSRIE[4:1] that corresponds to this port is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 0: Receive FEAC Idle Interrupt Enable (RFIIE) – This bit enables an interrupt if the RFIL bit is set and the bit
in
.PSRIE[4:1] that corresponds to this port is set.
0 = interrupt disabled
1 = interrupt enabled
Register Name:
FEAC.RFDR
Register Description:
FEAC Receive FIFO Data Register
Register Address:
0DCh
Bit
# 15 14 13 12 11 10 9 8
Name
-- -- -- -- -- -- -- --
Default
0 0 0 0 0 0 0 0
Bit
# 7 6 5 4 3 2 1 0
Name RFFI -- RFF5 RFF4 RFF3 RFF2 RFF1 RFF0
Default
0 0 0 0 0 0 0 0
Bit 7: Receive FEAC FIFO Data Invalid (RFFI) – When 0, the Receive FIFO data (RFF[5:0]) is valid. When 1, the
Receive FIFO data is invalid (Receive FIFO is empty).
Bits 5 to 0: Receive FEAC FIFO Data (RFF[5:0]) – These six bits are the FEAC code data stored in the Receive
FIFO. RFF[5] is the LSB (last bit received) of the FEAC code (C[6]), and RFF[0] is the MSB (first bit received) of the
FEAC code (C[1]). The Receive FEAC FIFO data (RFF[5:0]) is updated when it is read (lower byte read).