Rainbow Electronics DS3170 - Manual (Page 145)

DS3170 DS3/E3 Single-Chip Transceiver
145 of 233
must be changed to zero and back to one for another pattern to be loaded. Loading a new pattern will forces the
receive pattern generator out of the “Sync” state which causes a resynchronization to be initiated. Note: QRSS,
PTS, PLF[4:0}, PTF[4:0], and BSP[31:0] must not change from the time this bit transitions from 0 to 1 until four
receive clock cycles after this bit transitions from 0 to 1.
Bit 4: Receive Pattern Inversion Control (RPIC) – When 0, the receive incoming data stream is not altered.
When 1, the receive incoming data stream is inverted.
Bit 3: Manual Pattern Resynchronization (MPR) – A zero to one transition of this bit will cause the receive
pattern generator to resynchronize to the incoming pattern. This bit must be changed to zero and back to one for
another resynchronization to be initiated. Note: A manual resynchronization forces the receive pattern generator
out of the “Sync” state.
Bit 2: Automatic Pattern Resynchronization Disable (APRD) – When 0, the receive pattern generator will
automatically resynchronize to the incoming pattern if six or more times during the current 64-bit window the
incoming data stream bit and the receive pattern generator output bit did not match. When 1, the receive pattern
generator will not automatically resynchronize to the incoming pattern.
Bit 1: Transmit New Pattern Load (TNPL) – A zero to one transition of this bit will cause the programmed test
pattern (QRSS, PTS, PLF[4:0}, PTF[4:0], and BSP[31:0]) to be loaded in to the transmit pattern generator. This bit
must be changed to zero and back to one for another pattern to be loaded. Note: QRSS, PTS, PLF[4:0}, PTF[4:0],
and BSP[31:0] must not change from the time this bit transitions from 0 to 1 until four transmit clock cycles after this
bit transitions from 0 to 1.
Bit 0: Transmit Pattern Inversion Control (TPIC) – When 0, the transmit outgoing data stream is not altered.
When 1, the transmit outgoing data stream is inverted.
Register Name:
BERT.PCR
Register Description: BERT Pattern Configuration Register
Register Address: 062h
Bit
# 15 14 13 12 11 10 9 8
Name -- -- -- PTF4 PTF3 PTF2 PTF1 PTF0
Default 0 0 0 0 0 0 0 0
Bit
# 7 6 5 4 3 2 1 0
Name -- QRSS PTS PLF4 PLF3 PLF2 PLF1 PLF0
Default
0 0 0 0 0 0 0 0
Bits 12 to 8: Pattern Tap Feedback (PTF[4:0]) – These five bits control the PRBS “tap” feedback of the pattern
generator. The “tap” feedback will be from bit y of the pattern generator (y = PTF[4:0] +1). These bits are ignored
when programmed for a repetitive pattern. For a PRBS signal, the feedback is an XOR of bit n and bit y.
Bit 6: QRSS Enable (QRSS) – When 0, the pattern generator configuration is controlled by PTS, PLF[4:0], and
PTF[4:0], and BSP[31:0]. When 1, the pattern generator configuration is forced to a PRBS pattern with a
generating polynomial of x
20 + x 17 + 1. The output of the pattern generator will be forced to one if the next fourteen
output bits are all zero.
Bit 5: Pattern Type Select (PTS) – When 0, the pattern is a PRBS pattern. When 1, the pattern is a repetitive
pattern.
Bits 4 to 0: Pattern Length Feedback (PLF[4:0]) – These five bits control the “length” feedback of the pattern
generator. The “length” feedback will be from bit n of the pattern generator (n = PLF[4:0] +1). For a PRBS signal,
the feedback is an XOR of bit n and bit y. For a repetitive pattern the feedback is bit n.