Rainbow Electronics DS3170 - Manual (Page 10)

DS3170 DS3/E3 Single-Chip Transceiver
10 of 233
LIST OF TABLES
Table 4-1. Standards Compliance ............................................................................................................................. 16
Table 7-1. DS3170 Short Pin Descriptions ................................................................................................................ 25
Table 7-2. Detailed Pin Descriptions ......................................................................................................................... 27
Table 8-1. Configuration of Port Register Settings .................................................................................................... 52
Table 9-1. LIU Enable Table...................................................................................................................................... 57
Table 9-2. All Possible Clock Sources Based on Mode and Loopback..................................................................... 57
Table 9-3. Source Selection of TLCLK Clock Signal ................................................................................................. 58
Table 9-4. Source Selection of TCLKO (Internal Tx Clock)....................................................................................... 59
Table 9-5. Source Selection of RCLKO Clock Signal (Internal Rx Clock)................................................................. 59
Table 9-6. Transmit Line Interface Signal Pin Valid Timing Source Select ............................................................... 60
Table 9-7. Transmit Framer Pin Signal Timing Source Select .................................................................................. 61
Table 9-8. Receive Line Interface Pin Signal Timing Source Select ......................................................................... 61
Table 9-9. Receive Framer Pin Signal Timing Source Select ................................................................................... 62
Table 9-10. Reset and Power-Down Sources ........................................................................................................... 65
Table 9-11. CLAD Clock Source Settings ................................................................................................................. 66
Table 9-12. Global 8 kHz Reference Source Table................................................................................................... 67
Table 9-13. Port 8 kHz Reference Source Table....................................................................................................... 67
Table 9-14. GPIO Global Signals .............................................................................................................................. 68
Table 9-15. GPIO Pin Global Mode Select Bits......................................................................................................... 68
Table 9-16. GPIO Port Alarm Monitor Select ............................................................................................................ 69
Table 9-17. Loopback Mode Selections .................................................................................................................... 71
Table 9-18. Line AIS Enable Modes .......................................................................................................................... 75
Table 9-19. Payload (Downstream) AIS Enable Modes ............................................................................................ 75
Table 9-20. TSOFI Input Pin Functions ..................................................................................................................... 76
Table 9-21. TSOFO/TDEN/Output Pin Functions...................................................................................................... 76
Table 9-22 TCLKO/TGCLK Output Pin Functions..................................................................................................... 76
Table 9-23. RSOFO/RDEN Output Pin Functions..................................................................................................... 77
Table 9-24. RCLKO/RGCLK Output Pin Functions ................................................................................................... 77
Table 9-25. Framing Mode Select Bits FM[2:0] ......................................................................................................... 77
Table 9-26. Line Mode Select Bits LM[2:0]................................................................................................................ 78
Table 9-27. C-Bit DS3 Frame Overhead Bit Definitions ............................................................................................ 85
Table 9-28. M23 DS3 Frame Overhead Bit Definitions ............................................................................................. 87
Table 9-29. G.832 E3 Frame Overhead Bit Definitions ............................................................................................. 92
Table 9-30. Payload Label Match Status.................................................................................................................. 96
Table 9-31. Pseudo-Random Pattern Generation ................................................................................................... 109
Table 9-32. Repetitive Pattern Generation .............................................................................................................. 109
Table 9-33. Transformer Characteristics ................................................................................................................. 114
Table 9-34. Recommended Transformers............................................................................................................... 115
Table 10-1. Register Address Map .......................................................................................................................... 117
Table 11-1. Global Register Bit Map........................................................................................................................ 119
Table 11-2. Port Register Bit Map ........................................................................................................................... 119
Table 11-3. BERT Register Bit Map ........................................................................................................................ 120
Table 11-4. Line Register Bit Map .......................................................................................................................... 121
Table 11-5. HDLC Register Bit Map ........................................................................................................................ 121
Table 11-6. FEAC Register Bit Map ........................................................................................................................ 122
Table 11-7. Trail Trace Register Bit Map................................................................................................................. 123
Table 11-8. T3 Register Bit Map.............................................................................................................................. 123
Table 11-9. E3 G.751 Register Bit Map................................................................................................................... 124
Table 11-10. E3 G.832 Register Bit Map................................................................................................................. 125
Table 11-11. Global Register Map........................................................................................................................... 126
Table 11-12. Port Register Map............................................................................................................................... 133
Table 11-13. BERT Register Map............................................................................................................................ 144
Table 11-14. Transmit Side B3ZS/HDB3 Line Encoder/Decoder Register Map ..................................................... 151
Table 11-15. Receive Side B3ZS/HDB3 Line Encoder/Decoder Register Map ...................................................... 152
Table 11-16. Transmit Side HDLC Register Map .................................................................................................... 156
Table 11-17. Receive Side HDLC Register Map ..................................................................................................... 159
Table 11-18. FEAC Transmit Side Register Map .................................................................................................... 163