Rainbow Electronics DS26519 User Manual
General description, Applications, Functional diagram

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REV: 040907
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
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.
GENERAL DESCRIPTION
The DS26519 is a single-chip 16-port framer and line
interface unit (LIU) combination for T1, E1, and J1
applications. Each port is independently configurable,
supporting both long-haul and short-haul lines. The
DS26519 is nearly software compatible with the
DS26528 and its derivatives.
APPLICATIONS
Routers
Channel Service Units (CSUs)
Data Service Units (DSUs)
Muxes
Switches
Channel Banks
T1/E1 Test Equipment
FUNCTIONAL DIAGRAM
DS26519
T1/J1/E1
Transceiver
T1/E1/J1
NETWORK
BACKPLANE
TDM
x16
ORDERING INFORMATION
PART TEMP
RANGE
PIN-PACKAGE
DS26519G
0
°C to +70°C
484 HSBGA
DS26519G+
0
°C to +70°C
484 HSBGA
DS26519GN
-40
°C to +85°C
484 HSBGA
DS26519GN+
-40
°C to +85°C
484 HSBGA
+ Denotes lead-free/RoHS compliant device.
FEATURES
16 Complete T1, E1, or J1 Long-Haul/
Short-Haul Transceivers (LIU Plus Framer)
Independent T1, E1, or J1 Selections for Each
Transceiver
Software-Selectable Transmit- and Receive-
Side Termination for 100
Ω T1 Twisted Pair,
110
Ω J1 Twisted Pair, 120Ω E1 Twisted Pair,
and 75
Ω E1 Coaxial Applications
Hitless Protection Switching
Crystal-Less Jitter Attenuators Can Be
Selected for Transmit or Receive Path; Jitter
Attenuator Meets ETS CTR 12/13, ITU-T
G.736, G.742, G.823, and AT&T Pub 62411
External Master Clock Can Be Multiple of
2.048MHz or 1.544MHz for T1/J1 or E1
Operation; This Clock is Internally Adapted
for T1 or E1 Usage in the Host Mode
Receive-Signal Level Indication from -2.5dB
to -36dB in T1 Mode and -2.5dB to -44dB in E1
Mode in Approximate 2.5dB Increments
Transmit Open- and Short-Circuit Detection
LIU LOS in Accordance with G.775, ETS 300
233, and T1.231
Transmit Synchronizer
Flexible Signaling Extraction and Insertion
Using Either the System Interface or
Microprocessor Port
Alarm Detection and Insertion
T1 Framing Formats of D4, SLC-96, and ESF
J1 Support
E1 G.704 and CRC-4 Multiframe
T1-to-E1 Conversion
Features Continued in Section
DS26519
16-Port T1/E1/J1 Transceiver
www.maxim-ic.com
Document Outline
- TABLE OF CONTENTS
- 1. DETAILED DESCRIPTION
- 2. FEATURE HIGHLIGHTS
- 3. APPLICATIONS
- 4. SPECIFICATIONS COMPLIANCE
- 5. ACRONYMS AND GLOSSARY
- 6. MAJOR OPERATING MODES
- 7. BLOCK DIAGRAMS
- 8. PIN DESCRIPTIONS
- 9. FUNCTIONAL DESCRIPTION
- 9.1 Processor Interface
- 9.2 Clock Structure
- 9.3 Resets and Power-Down Modes
- 9.4 Initialization and Configuration
- 9.5 Global Resources
- 9.6 Per-Port Resources
- 9.7 Device Interrupts
- 9.8 System Backplane Interface
- 9.8.1 Elastic Stores
- 9.8.1.1 Elastic Stores Initialization
- 9.8.1.2 Minimum Delay Mode
- 9.8.1.3 Additional Receive Elastic Store Information
- 9.8.1.4 Receiving Mapped T1 Channels from a 2.048MHz Backplane
- 9.8.1.5 Mapping T1 Channels onto a 2.048MHz Backplane
- 9.8.1.6 Receiving Mapped E1 Transmit Channels from a 1.544MHz Backplane
- 9.8.1.7 Mapping E1 Channels onto a 1.544MHz Backplane
- 9.8.2 IBO Multiplexing
- 9.8.3 H.100 (CT Bus) Compatibility
- 9.8.4 Transmit and Receive Channel Blocking Registers
- 9.8.5 Transmit Fractional Support (Gapped Clock Mode)
- 9.8.6 Receive Fractional Support (Gapped Clock Mode)
- 9.8.1 Elastic Stores
- 9.9 Framers
- 9.9.1 T1 Framing
- 9.9.2 E1 Framing
- 9.9.3 T1 Transmit Synchronizer
- 9.9.4 Signaling
- 9.9.5 T1 Data Link
- 9.9.6 E1 Data Link
- 9.9.7 Maintenance and Alarms
- 9.9.8 Alarms
- 9.9.9 Error Count Registers
- 9.9.10 DS0 Monitoring Function
- 9.9.11 Transmit Per-Channel Idle Code Generation
- 9.9.12 Receive Per-Channel Idle Code Insertion
- 9.9.13 Per-Channel Loopback
- 9.9.14 E1 G.706 Intermediate CRC-4 Updating (E1 Mode Only)
- 9.9.15 T1 Programmable In-Band Loop Code Generator
- 9.9.16 T1 Programmable In-Band Loop Code Detection
- 9.9.17 Framer Payload Loopbacks
- 9.10 HDLC Controllers
- 9.11 Power-Supply Decoupling
- 9.12 Line Interface Units (LIUs)
- 9.13 Bit Error-Rate Test Function (BERT)
- 10. DEVICE REGISTERS
- 10.1 Register Listings
- 10.2 Register Bit Maps
- 10.3 Global Register Definitions
- 10.4 Framer Register Descriptions
- 10.4.1 Receive Register Descriptions
- Receive Idle Code Definition Registers 1 to 32
- Receive SLC96 Data Link Registers
- Received Sa7 Bits Register
- Received SaX Bits Register
- E1 Receive Digital Milliwatt Enable Registers 1 to 4
- Receive-Signaling Change of State Enable Registers 1 to 4
- RHPBA
- Receive-Signaling Reinsertion Enable Registers 1 to 4
- 0D4h, 0D5h, 0D6h, 0D7h + (200h x (n - 1)) + (2000h x [(n - 1) / 8]): where n = 1 to 16
- 10.4.2 Transmit Register Descriptions
- 10.4.1 Receive Register Descriptions
- 10.5 LIU Register Definitions
- 10.6 BERT Register Definitions
- 11. FUNCTIONAL TIMING
- 12. OPERATING PARAMETERS
- 13. AC TIMING CHARACTERISTICS
- 14. JTAG BOUNDARY SCAN AND TEST ACCESS PORT
- 15. PIN CONFIGURATION
- 16. PACKAGE INFORMATION
- 17. DOCUMENT REVISION HISTORY