Rainbow Electronics DS26504 User Manual
General description, Applications, Features
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REV: 070105
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GENERAL DESCRIPTION
The DS26504 is a building-integrated timing-supply
(BITS) clock-recovery element. It also functions as a
basic T1/E1 transceiver. The receiver portion can
recover a clock from T1, E1, 64kHz composite clock
(64KCC), and 6312kHz synchronization timing
interfaces. In T1 and E1 modes, the Synchronization
Status Message (SSM) can also be recovered. The
transmit portion can directly interface to T1, E1, or
64KCC synchronization interfaces as well as source
the SSM in T1 and E1 modes. The DS26504 can
translate between any of the supported inbound
synchronization clock rates to any supported
outbound rate. The DS26504 can also accept an 8kHz
as well as a 19.44MHz reference clock. A separate
output is provided to source a 6312kHz clock. The
device is controlled through a parallel, serial, or
hardware controller port.
APPLICATIONS
BITS Timing
Rate Conversion
FEATURES
§ Accepts 8kHz and 19.44MHz References in
Addition to T1, E1, and 64kHz Composite Clock
§ GR378 Composite Clock Compliant
§ G.703 2048kHz Synchronization Interface
Compliant
§ G.703 64kHz Option A & B Centralized Clock
Synchronization Interface Compliant
§ G.703 64kHz Japanese Composite Clock
Synchronization Interface Compliant
§ G.703 6312kHz Japanese Synchronization
Interface Compliant
§ Interfaces to Standard T1/J1 (1.544MHz) and E1
(2.048MHz)
§ Interface to CMI-Coded T1/J1 and E1
§ T1/E1 Transmit Payload Clock Output
§ Short- and Long-Haul Line Interface
§ Transmit and Receive T1 BOC SSM Messages
with Receive Message Change of State and
Validation Indication
§ Transmit and Receive E1 Sa(n) Bit SSM
Messages with Receive Message Change of State
Indication
§ Crystal-Less Jitter Attenuator with Bypass Mode
for T1 and E1 Operation
§ Fully Independent Transmit and Receive
Functionality
§ Internal Software-Selectable Receive and
Transmit Side Termination for
75Ω/100Ω/110Ω/120Ω/133Ω
§ Monitor Mode for Bridging Applications
§ Accepts 16.384MHz, 12.8MHz, 8.192MHz,
4.096MHz, 2.048MHz, or 1.544MHz Master
Clock
§ 64kHz, 8kHz, and 400Hz Outputs in Composite
Clock Mode
§ 8-Bit Parallel Control Port, Multiplexed or
Nonmultiplexed, Intel or Motorola
§ Serial (SPI) Control Port and Hardware Control
Mode
§ Provides LOS, AIS, and LOF Indications through
Hardware Output Pins
§ Fast Transmitter Output Disable through Device
Pin for Protection Switching
§ IEEE 1149.1 JTAG Boundary Scan
§ 3.3V Supply with 5V Tolerant Inputs and
Outputs
§ Pin and Software Compatible with the DS26502
and DS26503
ORDERING INFORMATION
PART TEMP
RANGE
PIN-PACKAGE
DS26504L
0°C to +70°C
64 LQFP
DS26504LN -40°C to +85°C 64 LQFP
DS26504
T1/E1/J1/64KCC BITS Element
www.maxim-ic.com
Document Outline
- FEATURES
- SPECIFICATIONS COMPLIANCE
- BLOCK DIAGRAMS
- PIN FUNCTION DESCRIPTION
- PINOUT
- HARDWARE CONTROLLER INTERFACE
- PROCESSOR INTERFACE
- T1 FRAMER/FORMATTER CONTROL REGISTERS
- E1 FRAMER/FORMATTER CONTROL REGISTERS
- I/O PIN CONFIGURATION OPTIONS
- T1 SYNCHRONIZATION STATUS MESSAGE
- E1 SYNCHRONIZATION STATUS MESSAGE
- LINE INTERFACE UNIT (LIU)
- LOOPBACK CONFIGURATION
- 64kHz SYNCHRONIZATION INTERFACE
- 6312kHz SYNCHRONIZATION INTERFACE
- JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT
- FUNCTIONAL TIMING DIAGRAMS
- OPERATING PARAMETERS
- AC TIMING PARAMETERS AND DIAGRAMS
- REVISION HISTORY
- PACKAGE INFORMATION