Lenze EVS9332xK - Manual (Page 182)

Function library
Function blocks
3.2.44 Digital frequency processing (DFSET)
3−154
l
EDSVS9332K−EXT EN 4.0
3.2.44 Digital frequency processing (DFSET)
Purpose
Conditions the digital frequency for the controller. Input of the stretch factor, gearbox factor, and
speed or phase trimming.
*
a
b
b
a
*
a
b
b
a
+
+
1
0
+
+
C0537
C0536/2
C0536/1
C0033 C0533
C0530
C0252
C0536/3
C0538/2
C0539
DFSET
DFSET-NOUT
+
-
DFSET-A-TRIM
DFSET-N-TRIM
DFSET-RAT-DIV
DFSET-RESET
DFSET-IN
DFSET-PSET
DFSET-VP-DIV
DFSET-POUT
DFSET-SET
C0538/3
+
+
C0253
C0531
C0535
C0532
3
1
2
1
X5/E4
X9/6,7
MCTRL-PHI-ACT
C0538/1
DFSET-0-PULSE
DFSET-ACK
C0522
C0524
C0520
C0527
C0526
* C0529
C0528/1
C0528/2
CTRL
DFSET-PSET2
C1258
DFSET-N-TRIM2
+
+
C0534
C0430/5
2
3
X5/E5
C0521
C0523
MCTRL-PHI-ACT
C0525
C1255
FB_dfset
Fig. 3−117 Digital frequency processing (DFSET)
Signal Source Note
Name Type DIS DIS format CFG List
DFSET−0−PULSE d C0538/1 bin C0525 2 HIGH = release of zero pulse synchronising
DFSET−N−TRIM a C0537 dec [%] C0524 1 Speed trimming in [%] of C0011
DFSET−N−TRIM2 phd C1258 dec [rpm] C1255 4 Speed trimming in [rpm] of C0011
DFSET−RAT−DIV a C0536//2 dec C0522 1 Numerator of gearbox factor 100 % = 16384 inc
DFSET−VP−DIV a C0536/1 dec C0521 1 Numerator of stretch factor 100 % = 16384 inc
DFSET−IN phd C0539 dec [rpm] C0520 4 Speed/Phase setpoint
DFSET−SET d C0538/3 bin C0527 2
·
HIGH = Set phase integrators to equal values
·
LOW−HIGH edge sets DFSET−PSET = 0
·
HIGH−LOW edge sets DFSET−PSET = current value
of MCTRL−PHI−SET
·
DFSET−SET has a higher priority than DFSET−RESET
DFSET−RESET d C0538/2 bin C0526 2
·
HIGH = sets position difference = 0
·
HIGH = sets DFSET−PSET and DFSET−PSET2 = 0
DFSET−A−TRIM a C0536/3 dec [inc] C0523 1 Phase trimming 100% = 16384 inc
DFSET−ACK d − − − − HIGH = synchronising is performed
DFSET−POUT phd − − − − Speed/Phase setpoint
DFSET−NOUT a − − − − in [%] of nmax (C0011)
DFSET−PSET ph − − − − Following error for phase controller
DFSET−PSET2 ph − − − − Phase setpoint 65536 inc = 1 revolution