Zilog Z16C30 User Manual

Page 99

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Z16C30 USC

SER

ANUAL

UM97USC0100

ILOG

5.19 DMA SUPPORT FEATURES

(Continued)

A channel loads the value from the TCLR into the Transmit
Character Counter, and enables or disables the TCC
accordingly, when one of the following occurs:

Software writes the Trigger Tx DMA (or Trigger Tx and
Rx DMA) command to the RTCmd field of the Channel
Command/Address Register (CCAR15-11), or

Software writes the Load TCC (or Load RCC and TCC)
command to RTCmd in the CCAR, or

Software writes the Purge Tx FIFO (or Purge Tx and Rx
FIFO) command to RTCmd in CCAR, or

The TxCtrlBlk field in the Channel Control Register
(CCR15-14) is 10, specifying a two-word Transmit
Control Block, and an external Transmit DMA control-
ler fetches (the second byte of) the second word
containing the new character count. Which is to say,
the channel fetches the count “through” the TCLR.

A channel loads the value from the RCLR into the Receive
Character Counter, and enables or disables the RCC
feature, when any of the following occur:

Software writes the Trigger Rx DMA (or Trigger Tx and
Rx DMA) command to the RTCmd field of the Channel
Command/Address Register (CCAR15-11), or

Software writes the Load RCC (or Load RCC and TCC)
command to RTCmd in the CCAR, or

Software writes the Purge Rx FIFO (or Purge Tx and Rx
FIFO) command to RTCmd in CCAR, or

The Receiver detects an opening Flag or Sync charac-
ter.

Once a channel has loaded the TCC or RCC with a non-
zero value (which enables the feature) it decrements the
counter for each character/byte written into the associated
FIFO. That is, the Transmitter decrements the TCC by 1 or
2 when software or an external Transmit DMA controller
loads transmit data into the TxFIFO. The Receiver decre-
ments the RCC by 1 for each character/byte that it transfers
from its shift register into the RxFIFO.

A non-zero TCLR value should represent the number of
characters to send, not including any Transmit Control
Block information, nor a CRC that the Transmitter gener-

ates. A non-zero RCLR value can be either all ones, or the
number of characters/bytes in a message or frame above
which the Receiver should interrupt, including any CRC
but not including any Receive Status Block information. For
frame or message-oriented applications in which there’s
no particular maximum received frame or message length,
the all-ones value simplifies computing the length of each
frame or message slightly. This value allows software to
obtain the frame length by simply ones-complementing
the value read from RCCR or from a Receive Status Block
in memory, rather than by subtracting it from the starting
value.

On the Transmit side

, software can read the value in the

TCC at any time from the Transmit Character Count Reg-
ister (TCCR), but writing the TCCR address has no effect.
Figure 5-14 shows a decoder that detects when the counter
contains 0001. When software or an external Transmit
DMA controller writes enough data into the TxFIFO so that
the TCC counts down to 0, the channel marks the character
that corresponds to decrementing from 1 to 0 as End of
Frame/End of Message. When this character gets to the
other end of the FIFO, the marking makes the Transmitter
conclude the frame appropriately. (Typically, it sends a
CRC and a closing Flag or Sync character after the marked
character.)

If software or an external Transmit DMA controller writes 16
bits to the TDR while the counter contains 0001, the
channel only puts the character on the D7-0 lines into the
TxFIFO — it ignores the data on D15-8. In a system in which
even-addressed bytes fall on D7-0 (e.g., a system based
on an Intel processor) this isn’t a problem. On the other
hand, in systems in which even-addressed bytes reside on
D15-8 (e.g., a system based on the Zilog Z8000 or 16C0x
or a Motorola 680x0) it can cause problems. In such
systems, if the last character of a frame falls at an even
address, software must copy the last character into the
subsequent odd address as well, before presenting the
buffer to the Transmit DMA controller.

The Transmitter suppresses its DMA request from the time
an external Transmit DMA controller places the EOF/EOM
character in the TxFIFO until the Transmitter sends it. When
software uses the Transmit Control Block feature, this
procedure ensures that the Transmit DMA controller doesn’t
load the control information for the next frame or message,
while the Transmitter still needs the values for the current
one.

UM009402-0201