Zilog Z16C30 User Manual

Page 125

6-6

Z16C30 USC

SER

ANUAL

UM97USC0100

ILOG

6.2 FLYBY VS. FLOWTHROUGH DMA OPERATION

(Continued)

Figures 6-3 and 6-4 illustrate flyby (single-cycle) opera-
tion. In addition to the Request signal from the device to the
DMA controller, there’s an Acknowledge signal from the
DMAC back to the device. The DMA controller performs
just one bus cycle for each piece of data transferred, in
which the address lines and standard bus control signals
tell the memory what to do to fulfill its part in the transaction.
But in addition to this signalling, the DMA controller asserts
the Acknowledge line to the device to tell it to perform its
part, i.e. to place data on the data lines for a write to
memory, or to capture data that’s being read from memory.

The main advantage of flyby mode is faster operation, but
there’s a price to be paid in greater design complexity.
Most DMA controllers place this burden mostly on the
device side, and try to make DMA cycles appear to the
memory as much like processor cycles as possible.

The USC’s Transmitters and Receivers can operate in
either mode, with one important covenant for flyby opera-
tion. Chapter 2 noted that only one among /DS, /RD, /WR,
/PITACK, and those /TxACK and /RxACK pins that are
used as DMA Acknowledge lines, may be asserted at the
same time. While system designers usually think of signals
like /DS, /RD, and /WR as being important only when
they’re qualified by assertion of /CS, the above restriction
is true regardless of the state of /CS.

Since the DMA controller typically asserts /DS or /RD or
/WR to the memory during a flyby DMA cycle, in order to
use flyby transfers

the system designer must provide

external logic that blocks /DS, or /RD and /WR, from
being asserted at the USC simultaneously with /TxACK
or /RxACK.

The simplest way to do this is with a logic gate

or two to keep the pin(s) high whenever the DMA controller
is in control of the system bus.

6.3 DMA REQUESTS BY THE RECEIVER AND TRANSMITTER

In general, a DMA controller only transfers data when the
associated device requests that it do so. To use either
flowthrough or flyby DMA operation with a USC Receiver or
Transmitter, connect the /RxREQ or /TxREQ pin to the
Request input of the DMA controller, and program the
RxRMode or TxRMode field (IOCR9-8 or IOCR11-10 re-
spectively) to 01. The 01 value makes the channel output
the Receiver’s or Transmitter’s DMA request on /RxREQ or
/TxREQ.

A USC channel asserts /TxREQ to the transmit DMA
controller as follows:

1a.

the Transmitter is enabled (in TMR1-0), and

1b.

TxRMode (IOCR11-10) is 01, and

1c.

the Transmitter isn’t sending the end of a frame, as
described below, and

1d.

the Transmitter isn’t waiting for a Trigger command,
as described below, and either

1e1.

the number of empty character positions in the
TxFIFO is larger than the DMA Request Level value
programmed into TICR15-8 after a “Select
TICRhi=TxREQ Level” command, or

1e2.

the USC channel is already asserting /TxREQ and
the TxFIFO isn’t full
OR,

from the time software writes a Trigger Channel
Load DMA command to the Channel Command/
Address register (CCAR), until a DMA transfer into
CCAR clears the ChanLoad bit (CCAR7).

Point 1c. reflects the fact that, in HDLC/SDLC, HDLC/
SDLC Loop, 802.3, or Transparent Bisync, the Transmitter

stops requesting further DMA transfers after the DMA
controller fetches the last character of one frame, until it
has sent that character and terminated the frame or mes-
sage. The Transmitter does this so that the possible
loading of the TCB information for a new frame doesn’t
affect sending the end of the preceding frame.

Point 1d. above applies when the Wait4TxTrig bit in the
Channel Control Register (CCR13) is 1 in HDLC/SDLC,
HDLC/SDLC Loop, 802.3, or Transparent Bisync. In this
case, after sending the end of a message or frame (and
thus leaving the “waiting to send the end of a frame” state
noted in 1c.), the Transmitter doesn’t assert
/TxREQ until software writes a “Trigger Tx DMA” command
to the RTCmd field of the Channel Command/Address
Register (CCAR15-11).

A USC Receiver asserts /RxREQ to an external DMA
controller when:

the Receiver is enabled (in RMR1-0), and

RxRMode (IOCR9-8) is 01, and

the Receiver isn’t waiting for a Trigger command as
described below, and either

D1.

the Receiver is forcing out completed frame(s) as

described below, or

D2.

the number of received characters in the RxFIFO is

larger than the DMA Request Level value programmed
into RICR15-8 after a “Select RICRhi=TxREQ Level”
command, or

D3.

the Receiver is already asserting /RxREQ, it did not
just complete forcing out a frame, and the RxFIFO still
has at least two characters in it on a 16-bit bus, or at
least one character in it on an 8-bit bus.

UM009402-0201