Zilog Z16C30 - Manual (Page 134)

7-6
Z16C30 USC ®
U SER ' S M ANUAL
UM97USC0100
Z ILOG
7.6 INTERNAL INTERRUPT OPERATION
Figure 7-4 presents a model of the typical internal structure
of the interrupt subsystem, for a source “s” that is of type
“t”. Note that the Figure represents a model of the USC’s
interrupt logic rather than the exact logic; it’s included only
as an aid to understanding the interrupt subsystem.
Each individual source has an associated register bit that
we’ll call its Interrupt Arm or IA bit. (Previous Zilog docu-
ments called this bit an Interrupt Enable or IE bit, but also
used the same term for another bit that applies to the entire
type. To distinguish between these two kinds of register
bits, this description will call the one that applies to the
individual sources “IA”.)
IA bits are fully under software control. When an IA bit is 1,
the associated source can cause an interrupt.
The sources are typically readable as register bits them-
selves, and may be derived from various kinds of logic,
such as logic that compares the fullness of a FIFO with a
threshold level at which to interrupt, or logic that detects
transitions of another register bit.
Each source and its IA bit are logically ANDed. A rising
edge on the logical OR of these terms, for all the sources
in the type, sets an “Interrupt Pending” (IP) bit for the type.
For USC family members, IP bits are set independently of
the state of the associated IUS bits, and are cleared to 0
only by software (or by Reset).
A close examination of Figure 7-4 will show that setting of
IP is delayed if an “armed” source comes true during an
interrupt acknowledge cycle, but that’s not particularly
important for understanding the USC’s interrupt subsystem.
A second register bit associated with each type is the
Interrupt Enable or IE bit. This bit is under full software
control. When an IE bit is 1, an interrupt can be requested
when the type’s IP bit is 1. Note that an IP bit can be set
while its associated IE bit is 0; if software then sets IE before
it clears the associated IP bit, an immediate interrupt can
result.
There is one more register bit for each type, called the
Interrupt Under Service or IUS bit. The interrupt logic sets
the IUS bit for a type to 1 during an interrupt acknowledge
cycle, if the daisy chain shows that it is the highest-priority
type that’s currently requesting an interrupt. (This may
includes types in higher-priority devices and higher-prior-
ity types within the channel.) Aside from a hardware or
software Reset, an IUS bit can only be reset to 0 by
software. This is typically done near the end of an interrupt
service routine for that type. During the execution of the
interrupt service routine for a given type, the type’s IUS bit
blocks interrupt requests from lower-priority types.
The And gate near the top of Figure 7-4 shows the actual
conditions for a type to request an interrupt. A type’s IP and
IE bits must both be 1, its IUS bit must be 0, and its
incoming “IEI” signal must be true. IEI true indicates that no
higher-priority type (on-chip or external) has its IUS bit set.
Finally, a Master Interrupt Enable (MIE) register bit for the
channel must be set to 1.
UM009402-0201