Zilog Z16C30 User Manual

Page 85

5-18

Z16C30 USC

SER

ANUAL

UM97USC0100

ILOG

5.14 HDLC/SDLC MODE

Software can select this mode for both the Transmitter and
the Receiver, by writing 0110 to the TxMode and RxMode
in the Channel Mode Register (CMR11-8 and CMR3-0).

In some sense this is the most important mode of the USC,
at least for new designs. It is similar to character-oriented
synchronous modes in that data characters follow one
another on the serial medium without any extra/overhead
bits, and are organized into blocks of data with CRC
checking applied to the block as a whole.

For HDLC and SDLC, the blocks of data are called "frames".
Uniquely recognizable 8-bit sequences called "Flags",
consisting of 01111110, precede and follow each frame.
HDLC/SDLC protocols ensure the uniqueness of Flags,
without imposing any restrictions on the data that can be
transmitted, by having the Transmitter insert an extra 0 bit
whenever the last six bits it has sent are 011111. A
Receiver, in turn, removes such an inserted zero bit when-
ever it has sampled 0111110 in the last seven bit times.

Besides Flags, HDLC and SDLC define another uniquely
recognizable bit sequence called an "Abort", consisting of
a zero followed by seven or more consecutive ones.
Depending on the exact dialect of HDLC or SDLC, and the
security desired in communicating an Abort, software can
program the Transmitter to send Aborts consisting of a
zero followed by either 7 or 15 consecutive ones.

On the Transmit side,

the two MSBits of the TxSubMode

field (CMR15-14) control what the Transmitter does if a
Transmit Underrun condition occurs, that is, if it needs
another character to send but the TxFIFO is empty:

CMR15-14

Underrun Response

Send an Abort consisting of 01111111

Send an Abort consisting of a zero
followed by 15 consecutive ones

Send a Flag

Send the accumulated CRC followed
by a Flag, that is, make the data
transmitted so far into a proper frame.

After sending the sequence specified by this field, the
Transmitter sends the next frame if software or the external
Transmit DMA controller has placed new data in the
TxFIFO. Otherwise it sends the Idle line condition specified
by the TxIdle field of the Transmit Command/Status Reg-
ister (TCSR10-8), as described later in 'Between Mes-
sages, Frames, or Characters'. That section also de-
scribes the conditions under which the Transmitter will
combine the closing Flag of one frame, and the opening

Flag of the next, into a single 8-bit instance. The same
section also describes a feature whereby software can
ensure that USCs manufactured after June 1993 send a
programmable minimum number of Flags between frames.

Software can make the Transmitter send an Abort se-
quence at any time, by writing the “Send Abort” command
to the TCmd field of the Transmit Command/Status Regis-
ter (TCSR15-12). If CMR 15-14 as described above is 01,
the Transmitter sends an extended Abort when software
issues this command; otherwise it sends the shorter Abort
sequence.

If CMR13 is 1, the Transmitter sends the Preamble se-
quence defined by the TxPreL and TxPrePat fields of the
Channel Control Register (CCR11-8), before it sends the
opening Flag of each frame.

If the TxIdle field (TCSR10-8) is 000 to select Flags as the
idle line condition, CMR12 selects whether consecutive
idle Flags share a single intervening 0. If CMR12 is 1, the
idle pattern is 011111101111110..., while if CMR12 is 0 it
is 0111111001111110... A Flag that opens or closes a
frame never shares a zero with an idle-line Flag, even if
CMR12 is 1.

On the Receive side

, when the receiver detects the

closing Flag of a frame, it marks the preceding (partial or
complete) character with RxBound status in the RxFIFO.
As described in later sections, this marking may set the
channel’s Received Data Interrupt Pending bit and thus
force an interrupt request on its /INT pin, and/or it may force
a DMA request on the /RxREQ pin.

The receiver automatically copes with single Flags be-
tween frames, and with shared zeroes between Flags, as
described above for the transmit side.

5.14.1 Received Address and Control Field
Handling

The RxSubMode field in the Channel Mode Register (CMR7-
4) determines how the Receiver processes the start of
each frame, i.e., whether it handles Address and/or Con-
trol fields. To the extent that the Receiver handles Address
or Control field(s), it always does so in multiples of 8 bits.
Thereafter it divides data into characters of the length
specified by the RxLength field of the Receive Mode
Register (RMR4-2). The Receiver interprets this field as
described below. (An “x” in a bit position means the bit
doesn’t matter.)

UM009402-0201