Zilog Z16C30 - Manual (Page 197)

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Z16C30 USC ®
U SER ' S M ANUAL Z
ILOG
UM97USC0100
0 of the data bus. Similarly, data to be written to the
high order byte (D15-8) should be on AD15-8. Re-
member, Little-Endian means that the least significant
byte has the lowest address, while Big-Endian means
that the most significant byte has the lowest address.
Q: Is there a problem when using the USC family running
Ethernet on a backplane if minimum node distances
are violated?
A: This question applies to the layer 1 device driver used
and is out of the scope of the Zilog USC family
specification.
Q: Which pins are used to perform indirect addressing?
A: Using register pointer addressing, you need one ad-
dress line for S//D (for the IUSC) or A//B (for the USC)
and one for D//C (i.e. address lines A2 and A1 respec-
tively), so each USC or IUSC takes 4 words or 8 bytes.
Q: When reading an 8-bit value on a 16-bit bus from a
USC family register and using a “Big Endian” micro-
processor (Motorola 68000), which half of the bus
does the value return on (D15-8 or D7-0)?
A: Regardless of the processor being big or little endian,
the USC family will return an 8-bit value on both halves
of the data bus. When writing an 8-bit value to a
register, the USC family interprets the U//L bit (CCAR:0)
as LittleEndian. Therefore, data to be written to the low
order byte (D7-0) of a register, should be put on AD7-
SERIAL & PROTOCOL QUESTIONS AND ANSWERS
Q: Does the USC family support a promiscuous receive
(receive all addresses) when using HDLC/SDLC?
A: Yes, this is the default case. No Rx address checking
is selected by programming in the Channel Mode
Register (CMR) bits D5-4=00.
Q: How many FM1 flags are needed to sync up the DPLL
on the USC? Is a flag-to-data transition required to
begin syncing?
A: The DPLL watches the RxD line for transitions. It
assumes that these transitions are either clock or data.
Depending on the position of the transitions within the
bit cell, adjustments are made in the phase of the DPLL
output clock to synchronize this output clock with the
assumed bit cell boundaries of the incoming data.
“Quick Sync” tells the DPLL that the VERY NEXT EDGE
it sees is the one to synchronize to; if this is not the case
the DPLL will have to see “n” correct edges before it
will be in sync. This “n” is 3 for X8, 6 for X16, and 12 for
X32. The time required to really get in sync in the worst
case is thus a function of the data encoding method
employed as well as the data on the line during the
process. The key issue is the number of “edges” the
DPLL sees on the RxD line. The DPLL is a feedback
system. It inherently tries to stay in sync. If the DPLL
happens to sync up on the wrong edge, over time it will
adjust to correct the situation, just like it tries to track a
varying input signal. There is no “secret” in this; it
operates just like the SCC DPLL except that it adjusts
a little faster when it’s way out of sync.
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