Zilog Z16C30 User Manual

Page 66

4-17

Z16C30 USC

SER

ANUAL

ILOG

UM97USC0100

4.11 THE /RXREQ AND /TXREQ PINS

The

RxRMode

and

TxRMode

fields of the I/O Control

XxRMode

Function of /XxREQ pin

Input pin

DMA Request output
(or Interrupt Request)

Low output

High output

Chapter 6 describes the DMA Request function, whereby
a channel signals an off-chip DMA controller when its
TxFIFO or RxFIFO reaches a programmed degree of
“readiness” for DMA data transfer.

Chapter 7 suggests another use for these pins if they’re not
used as DMA requests, namely as interrupt request out-
puts that are separate from /INT. This is advantageous in
a system in which the host processor and bus provide
multiple interrupt request levels and the software uses
them for nested interrupts. See 'Using /RxREQ and /TxREQ
as Interrupt Requests' in Chapter 7 for more details.

Software can program a channel to interrupt the host
processor on either or both edges on these pins, as
described in the earlier section 'Edge Detection and Inter-
rupts'. Typically such interrupts would be used for an input
pin, that is, when RxRMode or TxRMode is 00. Software
should write a 1 to the

RxRDn IA

TxRDn IA

bit in the

Status Interrupt Control Register (SICR11 or SICR9) to
make a channel detect falling edges on /RxREQ or
/TxREQ, and program

RxRUp IA

TxRUp IA

(SICR10 or

SICR8) to 1 to make it detect rising edges.

As described in Edge Detection and Interrupts, the

RxRL/U

TxRL/U

bit (MISR11 or MISR9) is 1 if the

channel has detected an enabled edge, until software
writes a 1 to the bit to clear it. The

/RxR

/TxR

bit (MISR10

or MISR9) reflects the state of the pin transparently while
the L/U bit is 0, but is frozen while the L/U bit is 1. A 0 in
MISR10 or MISR9 indicates a high on the pin, and 1
indicates a low.

4.12 THE /RXACK AND /TXACK PINS

The

RxAMode

and

TxAMode

fields of the Hardware

Configuration Register (HCR3-2 and HCR7-6 respectively)
control the function of these pins:

XxAMode

Function of /XxACK pin

General-purpose input

DMA Acknowledge input

Low output

High output

Chapter 6 describes the DMA Acknowledge function,
whereby an off-chip DMA controller signals a USC channel
that a “flyby” or single-cycle DMA operation is occurring in
response to the channel’s assertion of the corresponding
REQ pin, and that the channel should provide data on, or
capture data from, the AD pins.

The USC does not provide transition-detection, latching,
or interrupt capabilities for the /RxACK and /TxACK pins as
it does for most of the other signals described in this
chapter. Therefore, if these pins aren’t used as DMA
Acknowledge inputs, they can be used either for outputs
or for noncritical polled inputs.

The two LSBits of the Channel Command/Status Register
(CCSR1 and CCSR0) allow software to sense the state of
a channel’s ACK pins if they’re used as general-purpose
inputs. Figure 4-5 shows the CCSR. Its

/TxACK

and

/RxACK

bits are forced to 0 unless the corresponding

TxAMode or RxAMode field in the HCR is 00, in which case
the bit reads back as a 0 when the /TxACK or /RxACK pin
is high and 1 when the pin is low.

UM009402-0201