Zilog Z16C30 - Manual (Page 158)

8-3
Z16C30 USC ®
U SER ' S M ANUAL Z ILOG
UM97USC0100
8.5 DETERMINING THE DEVICE REVISION LEVEL
Zilog makes every effort to improve devices like the 16C30
while preserving compatibility with software developed on
earlier devices. Nonetheless, for some purposes (like
using new features) software needs to tell which revision of
the device it’s operating on, and behave differently for
different revisions.
The Test Mode Control Register (TMCR) is register number
00111 (typically addresses 0E-0F), and the Test Mode
Data Register (TMDR) is register 00110 (typically ad-
dresses 0C-0D). If software writes the value 31 (hex 1F) to
the TMCR and then reads the TMDR as a 16-bit word, a
USC manufactured prior to June of 1993 will return the hex
value 4453, while those manufactured after that time will
return 4D44. Reading bytes from the TMDR will return the
LSbyte (hex 53 or 40) for both odd and even addresses. If
there are future functional revisions to the device, they will
return some other value.
Software can use this feature to determine whether it can
use new features of later devices, such as the Purge Rx
command (described in the Commands section of Chap-
ter 5) and the UnderWait feature (described in the ‘Han-
dling Overruns and Underruns’ section of the same chap-
ter).”
8.6 TIPS AND TECHNIQUES
This section describes some of the common ways that
people have gotten in trouble using the USC, in hardware
and software.
8.6.1 Common Hardware Problems
H1. /DS OR (/RD and /WR), not both
External logic can drive /RD or /WR or /DS or /PITACK
during a bus cycle, but not more than one of them. This
restriction includes /TxACK and/or /RxACK if they’re used
as DMA Acknowledge signals. Unused signal(s) among
these can be connected together and to a pullup resistor
or to V
CC
.
H2. More pullups!
USC designs need a lot of pullup resistors, for various
reasons:
■ Unused inputs or I/Os: /IEI, /SITACK, /PITACK, /ABORT
■ Outputs tri-stated until USC initialized: /BUSREQ, /INT
■ Bus control signals that aren’t always driven by external
logic: /AS, R//W, /DS, /RD, /WR.
■ Serial inputs that aren’t driven by external logic in
some cases: /TxREQ, /RxREQ, /TxC, /RxC, /CTS,
/DCD.
H3. /WAIT//RDY neither open-drain nor rescinded
/WAIT//RDY is a totem-pole output. This can be a time-
critical signal, and RC rise times aren’t good in critical
applications. The /WAIT//RDY outputs of multiple USCs
have to be ORed (positive-logic ANDed) using a logic
gate.
H4. Drive /AS whenever /RD, /WR, or /DS
Designs that synthesize an /AS pulse to multiplex a non-
multiplexed bus (so that software doesn’t have to write
register addresses to indirect address registers) need to
pulse /AS low in all cycles that include a pulse on /RD, /WR,
or /DS. Several designers, including the writer, have gotten
in trouble trying to save power and noise by only driving
/AS low in host cycles targeted for the USC. It’s OK to do
this if /RD and /WR or /DS are similarly qualified, so that they
occur only during cycles targeted to the USC. But if the
logic blocks the /AS and then shows the part one of the
other strobes, it figures it’s still “chip selected” (after all,
didn’t the last /AS show /CS low?) and responds to the
cycle that’s actually intended for a different slave.
8.6.2 Common Software Problems
S0. “Unreset”
The software Reset facility in the CCAR has to be set and
then cleared. The part will not operate correctly if RTReset
(CCAR10) is left as 1.
S1. Register Initialization Order
There are certain constraints on the order in which the
various registers in the USC should be initialized, as
described earlier in this chapter. Many of them are com-
mon-sense points, but some “obvious” approaches, like
initializing the registers in address order or alphabetical
order, are not likely to succeed.
UM009402-0201