Zilog Z16C30 - Manual (Page 27)

2-1
Z16C30 USC ®
U SER ' S M ANUAL Z ILOG
UM97USC0100
2.1 INTRODUCTION
U SER ’s M ANUAL
C
HAPTER
2
B US I NTERFACING
The USC ® can be used in systems with various micropro-
cessor or backplane buses. Its flexibility with respect to
host bus interfacing derives from its Bus Configuration
Register (BCR), from on-chip logic that monitors bus
activity before software writes the BCR, and from certain
other registers in the serial channels. This section de-
scribes how to use these facilities to interface the USC to
a variety of host microprocessors and buses.
2.2 MULTIPLEXED/NON-MULTIPLEXED OPERATION
same as that used on the host bus (as with a Zilog 16C0x),
then the USC’s /AS pin can be directly connected to the
corresponding bus signal. Figure 2-1 shows such a sys-
tem.
Figure 2-1. Simple Multiplexed System
16C01
AD15:AD0
/AS
USC
AD15:AD0
/AS
One important distinction among buses is whether they
include separate sets of lines for addresses and for data,
or whether the same set of lines carries multiplexed ad-
dresses and data. On a multiplexed bus, the USC captures
addressing at rising edges on /AS. If this signaling is the
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