Zilog Z16C30 - Manual (Page 129)

7-1
Z16C30 USC ®
U SER ' S M ANUAL Z ILOG
UM97USC0100
7.1 INTRODUCTION
U SER ’s M ANUAL
C
HAPTER
7
I NTERRUPTS
The interrupt subsystem of the USC derives from Zilog’s
long experience in providing the most advanced interrupt
capabilities in the microprocessor field. These capabilities
can be used to their best advantage in a system including
a Zilog processor and other Zilog peripherals, but it’s easy
to interface the USC to interrupt other processors as well.
This chapter describes the USC’s interrupt capabilities
and how to use them in various system applications.
The USC dedicates eight pins to interrupts. Each channel
has its own interrupt request output (/INTA and /INTB). The
/SITACK and /PITACK inputs signal that the processor is
acknowledging an interrupt, in different ways for use with
different kinds of host microprocessors.
7.2 INTERRUPT ACKNOWLEDGE DAISY-CHAINS
Figure 7-1 shows an interrupt acknowledge daisy-chain.
The highest-priority daisy-chainable device that can re-
quest an interrupt has its IEI pin tied High. Because of this,
it can always request an interrupt, and it “has first claim at”
providing an interrupt vector in answer to an interrupt
acknowledge cycle. The IEO pin of the highest-priority
device is connected to the IEI pin of the next-higher-priority
device. This “daisy chaining” of IEO outputs to IEI inputs
continues until the lowest-priority daisy-chainable device
that can request an interrupt, which has its IEO pin left
unconnected.
With the USC as with all Zilog-compatible devices except
Z80
® family members, the IACK daisy chain serves two
separate functions. During an interrupt acknowledge cycle,
the daisy chain acts to select the highest-priority request-
For applications in which interrupt acknowledge cycles
cannot easily be detected at the USC, software can simu-
late such a cycle.
Each channel has its own Interrupt Enable In (IEIA, IEIB)
and Out (IEOA, IEOB) pins. These signals allow systems
including several Zilog-compatible peripherals to use an
Interrupt Acknowledge Daisy Chain to select how multiple
interrupting devices should be serviced. This can elimi-
nate the need for a separate interrupt controller. On the
other hand, because the USC provides separate Interrupt
Request outputs and Interrupt Enable inputs for each
channel, external interrupt control logic can process inter-
rupt requests in a round-robin or dynamic-priority fashion
among the channels in one or more USCs and/or other
peripheral devices.
ing device as the one to return an interrupt vector. After
that, until the resulting interrupt service routine is over, the
daisy chain serves to block interrupt requests from de-
vices having a lower priority than that of the one currently
being serviced, while allowing them from higher-priority
devices.
This daisy-chain structure allows nesting of interrupt ser-
vice routines. Nesting can greatly improve worst-case
interrupt response times for critical real-time applications
as well as I/O-intensive computing systems. Whether or
not host software uses nested interrupts, the USC’s inter-
rupt subsystem provides the most efficient interrupt han-
dling possible.
UM009402-0201