Zilog Z16C30 User Manual

Page 51

4-2

Z16C30 USC

SER

ANUAL

UM97USC0100

ILOG

4.3 TRANSMIT AND RECEIVE CLOCKING

The USC’s Receiver and Transmitter logic have separate
internal clock signals that we’ll call RxCLK and TxCLK. In
most of the USC’s operating modes, the Receiver samples
a new bit on RxD once per cycle of RxCLK, and the
Transmitter presents a new bit on TxD for each cycle of
TxCLK. One exception is asynchronous mode, in which
RxCLK and TxCLK run at 16, 32, or 64 times the bit rate on
RxD and TxD respectively. The other exception involves
Biphase-encoded serial data, for which the Receiver
samples RxD on both edges of RxCLK, and the Transmitter
may change TxD on both edges of TxCLK.

Figure 4-1 shows how RxCLK and TxCLK can be derived
in several different ways. This flexibility is an important part
of the USC’s ability to adapt to a wide range of applica-
tions.

In the simplest case, external logic derives clocks indicat-
ing bit boundaries, and software programs the channel to
take RxCLK directly from the /RxC pin and TxCLK directly
from the /TxC pin. When a channel uses such external
clocking for synchronous operation with “NRZ” data, it
samples a new bit on the RxD pin on each rising edge on
/RxC, and presents each new bit on the TxD pin on the
falling edge of /TxC.

It is often desirable to vary the bit rates for transmission and
reception by programming the USC, rather than by means
of off-chip hardware. To provide for this, each channel
includes independent means by which high-speed clock-
ing on /RxC or /TxC can be divided down to almost any
desired bit rate.

4.3.1 CTR0 and CTR1

There are two separate 5-bit counters called CTR0 and
CTR1 in each channel of a USC, comprising the “first
stage” of the channel’s clock-generation logic. Figure 4-2
shows the Clock Mode Control Register. Its

CTR0Src

and

CTR1Src

fields (CMCR13-12 and CMCR15-14 respec-

tively) control whether each counter runs and whether it
takes its input from the /RxC or /TxC pin:

CTRnSRC

CTRn clock source

CTRn disabled

Reserved (disabled)

CTRn input = /RxC pin

CTRn input = /TxC pin

Figure 4-3 shows the Hardware Configuration Register. Its

CTR0Div

field (HCR15-14) controls the factor by which

CTR0 divides its input to produce its output:

CTR0Div

CTR0 operation

CTR0 output = input/32

CTR0 output = input/16

CTR0 output = input/8

CTR0 output = input/4

There were not enough register bits to allow a separate
2-bit “CTR1Div” field. If the

CTR1DSel

bit in the Hardware

Configuration Register (HCR13) is 0, the CTR0Div field
determines the factor by which both CTR1 and CTR0
divide their inputs to produce their outputs. If CTR1DSel is
1, the DPLLDiv field in the Hardware Configuration Regis-
ter (HCR11-10) determines the factor by which both CTR1
and the DPLL divide their inputs to produce their outputs.
In either case, the channel interprets the selected 2-bit
field as shown above for CTR0Div.

The output of either counter can be used directly as RxCLK
and/or TxCLK. It can be used as the input to either of two
Baud Rate Generators called BRG0 and BRG1, and it can
be routed to the /RxC or /TxC pin.

4.3.2 The Baud Rate Generators

There are two 16-bit down counters called BRG0 and
BRG1 in each channel of a USC; they form the “second
stage” of the channel’s clock-generation logic. The

BRG0Src

and

BRG1Src

fields in the Clock Mode Control

BRGnSRC

BRGn clock source

CTR0 output

CTR1 output

/RxC pin

/TxC pin

UM009402-0201