Zilog Z16C30 - Manual (Page 136)

7-8
Z16C30 USC ®
U SER ' S M ANUAL
UM97USC0100
Z ILOG
7.7 DETAILS OF THE MODEL
The IA and IE bits appear near the left side of Figure 7-4,
as D-type flip-flops that capture the state of an AD line
when software writes a specific register. The IP bit appears
as a D-type flip-flop and a latch that are set “by hardware”
as described above; software can set and clear the latch.
The signal labelled /IACKcy is Low for the duration of an
interrupt acknowledge sequence. The IUS bit appears as
a D-type flip-flop that can be set via its clock and D inputs
at the end of an acknowledge cycle; again, software can
set or clear IUS.
The various signals named “SW op x”, that set and clear IP
and IUS, represent software operations. These may reflect
the writing of a “1” bit to a certain register bit position, or
may represent the writing of an encoded command to a
register. Since software always has to try to clear IP during
an interrupt service routine, and typically also has to clear
IUS, there are often several ways to clear these bits, as
shown by the multiple “SW op” signals for these functions
in the Figure. One thing not shown in the Figure is how the
typical command “Reset Highest IUS” is implemented —
including this function would have considerably increased
the complexity of the logic, which is already complex
enough!
The two downward-pointing gates in Figure 7-4 form the
type’s “IEO” output. They assert this output only if the
type’s incoming IEI is High and its IUS bit is 0. There is a
register bit “Disable Lower Chain” (DLC) in each channel;
if/when DLC is 1 the channel’s IEO is forced false/low. The
downward-pointing OR gate reflects the functional shift of
the daisy-chain during interrupt-acknowledge cycles. Its
output is High except during IACK cycles, at which time it
allows IEO to be asserted High only if this type is not
requesting an interrupt.
Finally, the signal labelled “Drive Vector” controls when the
channel places an interrupt vector on the data bus during
an interrupt acknowledge cycle. There is a register bit No
Vector (NV) in each channel; NV=1 prevents driving a
vector. The bus interface logic derives the signal “IACK
Read” from /RD, /PITACK or the combination of /DS Low
and R//W high. In most cases IACK Read is true during the
latter part of the time that /IACKcy is true. The channel
provides a vector on AD7-0 while IACK Read is true, if NV
is 0 and any of the types in the channel is the highest
priority interrupting type.
To keep its complexity reasonable, Figure 7-4 doesn’t
include the mechanism by which the content of a returned
interrupt vector can reflect the identity of the channel’s
highest-priority interrupting type.
UM009402-0201