Zilog Z16C30 User Manual

Page 154

7-26

Z16C30 USC

SER

ANUAL

UM97USC0100

ILOG

The hardware automatically tags the character that
corresponds to decrementing the TCC from 1 to 0.
After this character goes through the TxFIFO and out
onto the link, the Transmitter finishes the frame, typi-
cally by sending the CRC and closing Flag.

Software can either read the TCC or use its own length-
tracking mechanism, to know when each frame ends
and thus when to write the TCLR again.

Using 32-bit TCBs:
a.

Before the start of the first frame after a Reset, software
has to write a Purge TxFIFO or a Load TCC command
to the CCAR, to make the USC expect the first TCB.
(For subsequent frames this step isn’t necessary.)

At the start of each frame software should write a 32-
bit TCB to the TDR, of which the last 16 bits are the
number of data characters in the frame.

If, on a 16-bit bus after software has written enough
characters to the TDR to decrement the TCC down to
0001, software writes 16 bits to the TDR, the USC will
only place the single character from the AD7-0 pins
into the TxFIFO, ignoring the character on D15-8. In a
Little-Endian (Intel-type) system this is OK. In a Big-
Endian (Motorola-type) system software can avoid
problems by either copying the last character of each
Tx frame into the next-higher byte location after the
memory buffer, or by writing the last byte of the frame
using a byte write operation.

7.16.3 Handling a Type

(Continued)

Transmit Data Type
1.

Write the DCCR to clear the IP bit

2a.

Write the TDR often enough to bring the number of
empty bytes in the TxFIFO below the “Tx Data Interrupt
Request Level” in the TICR. OR,

2b.

Write the (TCSR and) TICR with a smaller Request
Level, to accomplish the same purpose. OR,

2c.

Write the ICR to disable the Transmit Data interrupt.

Typically the ISR wants to read the fill level from the TICR
and write the TDR enough times to fill the TxFIFO, or write
enough character pairs to fill it except for one empty
position. If there isn’t enough data available to do this, the
ISR might want to change the Request Level to 31 (hex 1F)
so that the next Transmit Data interrupt will occur when the
FIFO is empty, and then write all the available characters
to the TDR.

If the Request level is low and the serial rate is high, it might
happen that the Transmitter takes enough characters out
of the TxFIFO while software is writing the number indi-
cated by the initial read from the TICR, so that the number
of empty slots never falls below the Request Level. This is
particularly possible if the Request Level is 01 (meaning
interrupt when 2 empty slots) and software only writes
character pairs to the TDR. If this situation can happen,
after software finishes writing a block of data to the TDR, it
should read the TICR again time and write more data to the
TDR if needed, to ensure that future Tx Data interrupts will
occur.

In HDLC and similar modes, the part of the ISR that handles
Tx Data interrupts typically needs to take special actions at
the end of each frame. It can do this with or without using
the Transmit Character Counter (TCC), and can use the
TCC either directly or by means of the 32-bit Transmit
Control Block (TCB) feature.

Using the TCC directly:
a.

At the start of each frame software should load the
TCLR with the number of data characters in the frame/
message, and then write a Load TCC command to the
CCAR.

UM009402-0201