Zilog Z16C30 User Manual

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Z16C30 USC

SER

ANUAL

UM97USC0100

ILOG

5.22.4 DMA and Interrupt Request Levels

The USC channels continually compare the contents of the
Fill Level counters against two “threshold” levels for each.
Chapter 6 describes how the “Tx DMA Request Level”
determines how empty the TxFIFO must get before the
Transmitter starts requesting that an external Transmit
DMA controller should read more data from memory. Once
the Transmitter has started to request DMA transfer, it
typically keeps doing so until the DMA controller has filled
the TxFIFO or until the Transmit Character Counter has
counted down to zero.

Chapter 6 also describes how the “Receive DMA Request
Level” controls how full the RxFIFO should get before the
Receiver starts requesting that an external Receive DMA
controller should move data to memory. Once the Receiver
has started to request DMA transfer, it typically keeps
doing so until the DMA controller has emptied the RxFIFO,
or until it has stored the last character of a frame or
message.

Chapter 7 describes how, if software enables “Transmit
Data” interrupts, the “Transmit /INT Level” controls how
empty the TxFIFO should get before the Transmitter starts
requesting such an interrupt. It also describes how, if
software enables “Receive Data” interrupts, the “Receive
/INT Level” controls how full the RxFIFO should get before
the Receiver starts requesting such an interrupt. Software
doesn’t use these kinds of interrupts in USC applications
in which external Transmit and Receive DMA controllers
handle the data. But if software does use data interrupts,
the interrupt service routine should fill the TxFIFO or empty
the RxFIFO completely each time it executes. (As a mini-
mum the ISR should transfer enough data to bring the FIFO
status below the threshold level, or should raise the thresh-
old level to accomplish the same thing.)

5.22.3 Fill Levels

Each channel maintains a counter for each FIFO that
reflects its current contents. Software can read the number
of received characters/bytes that are currently in the
RxFIFO. To do this, it may first have to write the “Select
RICRHi=FIFO Status” command to the RCmd field of the
Receive Command/Status Register (RCSR15-12). Then
software can read the MSByte of the Receive Interrupt
Status Register (RICR15-8). The resulting 8-bit value rep-
resents the number of received characters in the RxFIFO.
It ranges from 0 for an empty RxFIFO to 32 for a full one.
Software can skip the step of writing the Select command
if it hasn’t written any of the other “Select RICRHi=...”
commands to the RCSR since the last time it issued this
command.

Similarly, software can read the number of entries that are
currently empty in the TxFIFO. It may first have to write the
“Select TICRHi=FIFO Status” command to the TCmd field
of the Transmit Command/Status Register (TCSR15-12).
Then software should read the MSByte of the Transmit
Interrupt Status Register (TICR15-8). The resulting 8-bit
value represents the number of empty positions in the
TxFIFO. It ranges from 0 for a full TxFIFO to 32 for an empty
one. As on the Receive side, software can skip the step of
writing the Select command if it hasn’t written any of the
other “Select TICRHi” commands to the TCSR since the
last time it issued this command.

Code that reads a FIFO Fill Level must ensure that no
interrupts will occur between the time it writes the “Select
xICRHi=FIFO Status” command to the TCSR or RCSR, and
when it reads the value from the TICR or RICR, if such
interrupts can lead to other code writing a different Select
command to the same Command/Status Register.

Large values of the FIFO Fill Levels indicate exceptional
conditions. 33 (hex 21) in the Rx Fill Level indicates that
data has been lost because of a Receive Overrun condi-
tion. Rx Fill Level values above that, particularly 63 (hex
3F), indicate that software read more data from the RxFIFO
than was received. Tx Fill Levels between 33 (hex 21) and
63 (hex 3F) inclusive indicate that software wrote more
data to the TxFIFO than there was room for. All of these
situations should be handled by issuing a Purge FIFO
command, although receive software may want to handle
an Overrun by reading out the FIFO first, to salvage data
received before the problem occurred.

UM009402-0201