Zilog Z16C30 User Manual

Page 30

2-4

Z16C30 USC

SER

ANUAL

UM97USC0100

ILOG

2.4 BUS WIDTH

Another major difference among host buses is the number
of data bits that can be transferred in one cycle. Software
can configure the USC to transfer 16 bits at a time, in which
case it is still possible to transfer 8 bits when this is
necessary or desirable. Or, software can restrict operation
to transferring only 8 bits at a time, on the AD7-AD0 pins.

This leaves the AD15-AD8 pins unused: another BCR
option allows them to carry register addresses. The latter
option allows software to directly address USC registers
even on a non-multiplexed bus, without having to write an
address into the USC before it accesses a register.

2.5 ACK VS. WAIT HANDSHAKING

The final major difference among host buses involves the
nature of the handshaking signals that slave devices use
for speed-matching with masters. Figure 2-6 illustrates the
three variations in common use. In the first, which we’ll call
Wait signaling, if a master selects a slave and the slave
cannot capture write data or provide read data within the
time allowed to keep the master operating at full speed, it
quickly (combinatorially) drives a Wait output low, and then
returns it to high when it’s ready to complete the cycle.
Some peripheral devices have Wait outputs that are open-
collector or open-drain, which can be tied together for a
negative logic wired-Or function. Because the USC drives
its /WAIT//RDY output high or low on a full-time basis, a
logic gate must be used to negative-logic OR (positive-
logic AND) its /WAIT//RDY output with the /WAIT signal(s)
for other slaves, to produce the /WAIT input to the master
(e.g., to the processor).

In the second scheme, “Acknowledge” signaling, all slaves
must respond when the master directs a cycle to them, by
driving an Acknowledge signal (sometimes called /DTACK)
low to allow the master to complete the transfer, and
keeping it low until the master does so. As with the previous
scheme, some peripherals provide slave Ack outputs that
are open-collector or open-drain, which can be tied to-
gether for a negative logic wired-Or function. Because the
USC drives its /WAIT//RDY output high or low on a full-time
basis, a logic gate must be used to negative-logic OR its
/WAIT//RDY output with the /ACK signals for other slaves,
to produce the Acknowledge input to the master.

In the third scheme, “Ready” signaling, all slaves must
respond when the master directs a cycle to them, by
driving a Ready signal high to allow the master to complete
the transfer, and keeping it high until the master does so.
This scheme differ from Wait signaling in the default state
of the handshaking signal between cycles (high for Wait
signaling, low for Ready). It has similar timing as Ack
signaling, but differs in the polarity of the handshaking
signal. With Ready signaling, the board designer must
include a logic gate to positive-logic OR the various slaves’
Ready lines to produce a composite Ready input for the
bus master(s).

The USC supports Acknowledge and Ready signaling for
all cycles, and Wait signaling for interrupt acknowledge
cycles. The USC register access times should be short
enough to avoid the need for Wait signaling on all but the
fastest processors. The board designer can combine the
USC’s /WAIT//RDY output with similar signals from other
slaves, by means of an external logic gate or (for Acknowl-
edge and Wait) an external tri-state or open-collector
driver.

If software writes the Bus Configuration Register (BCR) at
an address that makes the A//B pin low, the USC drives
/WAIT//RDY low as an “Acknowledge” signal, while if
software writes the BCR with A//B high, the USC drives
/WAIT//RDY as a “wait” signal.

UM009402-0201