Zilog Z16C30 User Manual

Page 190

8-35

Z16C30 USC

SER

ANUAL

ILOG

UM97USC0100

"TxFIFO Status" if last TCSR15-12 command 4-7 was 5
"Tx/Int level" if last TCSR15-12 command 4-7 was 6
"TxREQ level" if last TCSR15-12 command 4-7 was 7

Transmit Interrupt Control Register (TICR)

Register Address 0 b 11011

Pre

Sent IA

Bit(s)

Field/Bit

Name

Conditions

/Context

Description

Status

Ref Chapter: Section

Idle

Sent

Abort

Sent

EOF/
EOM

Sent IA

CRC

Sent

Wait2

Send

Under

TC1R

Sel

TICR15-8

the number of empty character/byte/octet
entries in the TxFIFO, above which to request
Transmit DMA transfer

6: DMA Requests by the
Receiver and Transmitter

7 written to
TCmd
(TCSR15-
12) since 5
or 6 written
there

TICR15-8

the number of empty character/byte/octet entries
in the TxFIFO, above which to request a Transmit
Data Interrupt

7: Transmit Data interrupts

6 written to
TCmd
(TCSR15-
12) since 5
or 7 written
there

TICR15-8

the number of empty character/byte/octet entries
currently in the TxFIFO

5:The Data Registers
and the FIFOs

5 written to
TCmd
(TCSR15-
12), or
Reset,
since 6 or 7
written
there

TICR7

1=arm interrupts on Preamble Sent (TCSR7)

7: Transmit Status Interrupt
Sources and IA Bits

PreSent IA

TICR6

1=arm interrupts on IdleSent (TCSR6)

IdleSent IA

TICR5

1=arm interrupts on AbortSent (TCSR5)

AbortSent
IA

TICR4

1=arm interrupts on EOF/EOM Sent (TCSR4)

EOF/EOM
Sent IA

TICR3

1=arm interrupts on CRCSent (TCSR3)

CRCSent IA

5: Synchronizing Frames/
Messages with Software
Response

TICR2

1=hold Transmitter from sending each
frame/message until software issues "Send
Message/Frame" command

Wait2Send

7: Transmit Status Interrupt
Sources and IA Bits

TICR1

1=arm interrupts on TxOver (TCSR1)

TxUnder IA

TICR0

0=select Time Constant value for reading TC1R;
1=capture current count for reading TC1R

TC1R Sel

4: Tx and Rx Clocking: The
Baud Rate Generators

Sync

H/SDLC

Sync

RW = Read/Write, RO = Read Only, WO = Write Only – for other codes see p. 8-10.

UM009402-0201