Zilog Z16C30 - Manual (Page 45)

3-1
Z16C30 USC ®
U SER ' S M ANUAL Z ILOG
UM97USC0100
3.1 INTRODUCTION
U SER ’s M ANUAL
C
HAPTER
3
A S AMPLE A PPLICATION
Figures 3-1 and 3-2 are schematics of a simple USC ®
application. It includes a USC, an 80186 integrated pro-
cessor, two EPROMs, two static RAMs, and 3 serial inter-
faces.
Figure 3-1 includes everything but the serial interfaces.
The processor U2 and oscillator X1 et al typically operate
at 16 MHz, and provide a 16 MHz SYSCLK that’s included
in the jumper blocks on the right side of p.2, so that it can
be jumpered into the /TxC or /RxC pin and thus be used for
baud rate generation. The 80186' bus features multiplexed
address and data so that software doesn’t have to write
register addresses into CCAR.
U7-9 are octal latches that capture the address from the
186 and present the latched address to the RAMs and
EPROMs. The EPROMs are selected by the Upper Chip
Select (/UCS) output of the 186, while the RAMs are
selected by the Lower Chip Select (/LCS) output. The USC
resides in I/O space, one channel being selected by the
first of the 186' Peripheral Chip Select outputs (PCS0) and
the other channel being selected by the other (PCS1).
The 28-pin EPROM sockets are set up to accept 2764’s,
27128’s, 27256’s, or 27512’s. The 32-pin RAM sockets can
accept 32-pin 128Kx8 or 28-pin 32Kx8 static RAMs.
The U10 74FCT240 inverts signals between active-high
signals on the 186 and active-low signals on the USC. The
/TxREQ and /RxREQ pins of USC channel A are inverted to
make the DMA Request 0 and 1 inputs of the 80186'
integrated DMA channels. This means that USC channel A
can use DMA operation while USC channel B must be
interrupt-driven or polled. Since the 186' DMA channels
use flow-through (two cycle) operation, channel A’s
/TxACK and /RxACK pins are free for use in the serial
interfaces.
UM009402-0201