Zilog Z16C30 - Manual (Page 115)

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Z16C30 USC ®
U SER ' S M ANUAL
UM97USC0100
Z ILOG
5.23 HANDLING OVERRUNS AND UNDERRUNS (Continued)
3. On an USC manufactured after June of 1993, write a
“Purge Rx” command to the CCAR. On an earlier
device, write a “Purge Rx FIFO” command to the
CCAR and write a 1 to the “Clear RCCF” bit in the
CCSR.
4. Reprogram the Rx DMA channel (if used) to point to
the start of the frame in which the overrun occurred.
5. Start the Rx DMA channel (if used)
6. If the Overrun condition is armed for interrupt, write a
1 to RCSR1 to clear the status bit.
7. If Overrun and other conditions are armed to cause
Receive Status interrupts, clear all the IA bits in the
RICR and then restore those that should be Armed.
5.23.3 Rx Overrun "Scribbling"
USCs manufactured prior to June of 1993 have a special
problem with Rx Overruns. When the end of a frame or
message arrives, the USC sets an internal state that forces
the Rx DMA request to store the end of the frame. Normally,
this state is cleared when the software or the Rx DMA
channel reads the last character of the frame from the
RDR/RxFIFO. However, if a frame ends while the Receiver
is overrun, the logic sets the internal state as usual, but
there’s nowhere to store the RxBound character that will
clear this state. The result is that the Receiver keeps
requesting that the Rx DMA channel store data, and
providing the entire contents of the RxFIFO again and
again, until the Rx DMA channel runs out of buffers to store
into, or until software responds to the overrun condition
and stops the scribbling by purging the RxFIFO.
However, the scribbling activity itself handicaps the pro-
cessor from executing the interrupt service routine effi-
ciently until the Rx DMA channel runs out of buffers. If it’s
important to stop the scribbling ASAP:
1. Use any resources provided in the DMA controller to
limit its activity in each period of bus control.
2. Give interrupts from the USC the highest possible
priority.
If the DMA controller provides bandwidth-limiting means,
the first step should allow the processor enough band-
width to slowly execute the ISR and terminate the scrib-
bling.
5.23.4 Fill Level Correctness and Extra
Bytes
With USCs manufactured before June 1993, certain worst-
case interarrivals of serial clocking and bus timing could
result in transient states in which the RxFIFO and TxFIFO
counts were incorrect. When software read these counts
and transferred data to the TDR or from the RDR, it could
work around such problems by the classic data acquisition
technique of reading a count until two successive readings
agreed. USCs manufactured after June 1993 include
logical interlocks so that these counts will always be
correct and need only be read once.
These interlocks have also eliminated a related problem, in
which a received character was completed just as a USC
Receiver was deciding to withdraw its Receive DMA re-
quest because the external Rx DMA controller had emp-
tied the RxFIFO. Under worst-case interarrivals, the logic
would maintain the request on a 16-bit bus even though the
RxFIFO contained only a single newly-received character.
The DMA channel would then do a 16-bit transfer, so that
the observable symptom of the problem was that occa-
sionally, “extra characters” would appear in the received
data stream. Such phenomena will not occur with USCs
manufactured after June 1993.
UM009402-0201