Zilog Z16C30 - Manual (Page 201)

B-7
Z16C30 USC ®
U SER ' S M ANUAL Z
ILOG
UM97USC0100
Q: Does the Purge Rx FIFO command clear the Receive
Character Counter?
A: No, the Purge Rx FIFO command does not clear the
Receive Character Counter, but it does cause the
contents of the RCLR to be loaded into the receive
character counter.
Q: What are the wiring concerns when connecting mul-
tiple IUSCs together?
A: Unless addresses are multiplexed onto the AD pins
with data, don’t connect the /AS pins of the IUSC’s to
any signal from or derived from the processor or
backplane bus. Instead connect them all together and
connect a pullup resistor to keep the line high when the
CPU has control of the bus.
The decoding logic that drives /CS should ensure that
no IUSC’s /CS pin can go low when another IUSC is in
control of the bus. Also the /INTACK pins must stay
high when an IUSC is in control of the bus.
Always connect all of the /UAS and /AS pins of the
IUSC’s together and use them to latch addresses from
the AD15-0 lines. Put a pullup resistor on /UAS to keep
the line high when the CPU has control of the bus.
Either connect all of the /DS pins together or all of the
/RD and /WR pins, but not all three. If all three are
interconnected, the first time one of the IUSCs be-
comes bus master and drives /DS and /RD or /DS and
/WR low, it will inactivate all of the other IUSCs. Provide
separate pullup resistors for each of the /DS pins or for
each of the /RD and /WR pins, whichever signals are
not used in the host bus.
Q: Can the /TxC pin be used for both data recovery in the
Rx data stream as well as clocking the transmit data?
A: Typically in this situation, while the DPLL is supplying
the receive clock, one of the counters (CTR0 or CTR1)
will be used to supply a fixed transmit clock at the
same rate. The problem with using the DPLL output to
drive the transmitter is that once the receive data
stream stops, the DPLL output may stop also, depend-
ing on the mode. Note that in HDLC Loop applications
it is necessary to use the DPLL outputs to drive both the
receiver and transmitter to prevent bit errors due to
timing differences between the different stations on
the loop.
Q: When using data encoding, the USC family specifies
the /TxC to TxD output delay at 35 ns max., for both
rising and falling edge of clock. What is the maximum
expected difference between /TxC rise to TxD out and
/TxC fall to TxD out.
A: These two delay times are matched very closely for
any specific device, due to the inherent matching
within a semiconductor device.
Q: When using the USC family in 16-bit multiplexed mode
and directly addressing the transmit and receive data
registers, is it necessary to use the D//C pin?
A: No, on the USC in multiplexed mode, one would tend
to ground the D//C pin. But do not carry this idea over
to IUSC applications, in which D//C is needed to select
between the DMA channels for access to their (non-
shared) registers.
Q: Why is the following General Timing specified:
T3 TsTxd(RxCf) RxD to /RxC Fall Setup Time?
T4 ThRxD(RxCf) RxD to /RxC Fall Hold Time?
A: For NRZ, NRZB, NRZI-Mark and NRZI-Space
encodings, these specifications are not applicable.
However, for all of the Biphase encodings, where the
receive data signal may change on both edges of the
clock, the receiver must sample the RxD pin on both
edges of the clock. Hence these two specifications.
Q: Can any data encoding method be used in Async
mode?
A: No, only NRZ can be used, for the simple reason that
in Async the receiver is looking for a 1-to-0 transition to
start the counting of receiver clocks to do the X16, X32
or X64 clock dividing. NRZ is the only encoding
method that can guarantee this edge polarity for a start
bit.
Q: How many receive clocks are required after the clock
that samples the last zero in a closing Flag to get the
last byte of data into the receive FIFO?
A: Three receive clocks, after receipt of the closing Flag,
are required to get the last byte of data into the receive
FIFO.
Q: What can cause the receiver to miss generating
RxBound interrupts? Depending on the FIFO Request
Level, the RxBound interrupt seems to be missing on
either odd-length or even-length frames.
A: The software is not setting the WordStatus bit in the
RICR. What happens is that the interrupt logic is then
seeing only the status on one byte when a word is read
from the receive FIFO. This leads to missing status
interrupts.
UM009402-0201