Zilog Z16C30 User Manual

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5-51

Z16C30 USC

SER

ANUAL

ILOG

UM97USC0100

5.24.3 Synchronous Reception

Between the end of one message or frame and the start of
the next, the Receiver goes through states that are similar
to the inter-message or inter-frame activities that are de-
scribed above for the Transmitter. As described in the
earlier section 'Status Reporting', software can use some
or all of the following status bits to track these state
changes: RxBound (RCSR4), CRCE/FE (RCSR3),
IdleRcved (RCSR6), and ExitedHunt (RCSR7). If the DPLL
is used, Chapter 4 describes the DPLLSync bit in the
Channel Command/ Status Register (CCSR12) which bears
a certain symmetry with the PreSent bit on the Transmit
side. Chapter 7 describes how software can enable the
RxBound, IdleRcved, and/or Exited Hunt conditions to
cause an interrupt.

The IdleRcved logic isn’t as flexible as the corresponding
TxIdle logic in the Transmitter, in that it only detects an Idle
condition consisting of 15 or 16 consecutive ones.

In HDLC/SDLC mode the Receiver automatically copes
with single Flags between frames and with shared zeroes
between Flags (011111101111110).

5.25 SYNCHRONIZING FRAMES/MESSAGES WITH SOFTWARE RESPONSE

In some applications, software can simply set up DMA
buffers for multiple frames or messages, and set the USC’s
Transmitter and/or Receiver and external DMA controller(s)
into operation to send and/or receive all of them. In other
applications, software has to interact with and supervise
the communications process more closely. (The extreme
case is when software has to check status register bits for
each character that it transfers to the TxFIFO or from the
RxFIFO.)

The USC provides two alternatives for interlocking the start
of transmission of a frame or message with software
response, and one similar interlock on the receive side.

Note that all three of these interlocks apply only after the
end of a frame, not before the first frame sent or received.

If the

Wait2Send

bit in the Transmit Interrupt Control

Register (TICR2) is 1, then each time the Transmitter
finishes sending a frame and before it sends the next, it
waits for software to write the Send Frame/Message com-
mand to the TCmd field of the Transmit Command/Status
Register (TCSR15-12). Depending on the programmed
mode the Transmitter may then go on to send the Preamble
or the opening Sync or Flag. This kind of interlock allows
the software to reprogram global Transmitter parameters
that may need to change between frames or messages. It
allows an external Transmit DMA controller (or software) to
fill the TxFIFO in preparation for the next frame or message,
before software issues the Send Frame/ Message com-
mand. One use for this interlock would be to change the
TxCRCatEnd bit in the Transmit Mode Register (TMR8)
between frames, in an application in which the Transmitter
should calculate a CRC in some messages or frames but
not in others.

If the

Wait4TxTrig

bit in the Channel Control Register

(CCR13) is 1, then each time the Transmitter finishes
sending a frame and before it sends the next, it waits for
software to issue the Trigger Tx DMA (or Trigger Rx and Tx
DMA) command before it requests DMA operation. This is
a “more stringent” interlock than the preceding one, in that
the external Transmit DMA controller won’t fill the TxFIFO
in preparation for the next frame, until software issues the
command. This kind of interlock is useful if DMA-related
parameters, or parameters that go through the TxFIFO with
the data, need to be changed between frames. The most
obvious example is reprogramming the buffer location and
length in the Transmit DMA controller.

On the Receive side, if the

Wait4RxTrig

bit in the Channel

Control Register (CCR5) is 1, then after an external Re-
ceive DMA controller has written a character marked as
RxBound to memory (and after it has written the Receive
Status Block if software has enabled this feature) the
Receiver doesn’t assert /RxREQ to the Receive DMA
controller again until software writes the Trigger Rx DMA
(or Trigger Rx and Tx DMA) command to the RTCmd field
of the Channel Command/Status Register (CCAR15-11).
Software can use this interlock to reprogram the Receive
DMA controller between frames.

UM009402-0201