Zilog Z16C30 - Manual (Page 159)

8-4
Z16C30 USC ®
U SER ' S M ANUAL Z ILOG
UM97USC0100
8.6.2 COMMON SOFTWARE PROBLEMS (Continued)
S2. WordStatus problems
In general, software wants to program the WordStatus bit
(RICR3) the same as BCR2, which indicates whether your
application uses a 16-bit bus. If software or the Rx DMA
channel sometimes read bytes and sometimes words from
the RDR/RxFIFO, change WordStatus as necessary be-
fore each access. If software writes the LSbyte of RICR to
change the Rx Status IA bits, be sure it preserves the
proper setting of WordStatus while doing so.
S3. Transmit Data Length
Note that in applications that use a DMA controller on the
Transmit side, there are typically two controls required on
the length of transmitted data. The Tx DMA channel typi-
cally has a register that controls how many bytes the DMA
channel takes from each buffer. This value must include
any Transmit Control Blocks that are provided in DMA
buffers.
The TCLR in the Transmitter, which is typically set from the
second word of the TCB if TCBs are used, controls how
many bytes the Transmitter sends in each frame, and
should not include CRC bytes that the Transmitter calcu-
lates and sends, but should include CRC bytes that are
“passed through” from a received frame without change.
S4. Receive Data Length
There is one required control, one optional control, and
one reporting mechanism associated with the length of
received data. The Rx DMA channel typically includes a
register that controls the (maximum) number of bytes the
channel will store in each buffer. The length of Rx memory
buffers, and thus values for said Rx DMA channel register,
should allow for storing CRCs if they’re used, and also
allow for RSBs if they’re stored in the buffer.
The optional control is the value of the RCLR, which can be
set to the length of the longest frame that can be legally
received, including the CRC. An optional interrupt when
the RCC underflows can be enabled to notify software of an
unduly long frame, which generally indicates the corrup-
tion of the Flag(s) between two frames.
The reporting mechanism is the ending value of the RCC
for each frame, which can be read by software from the
RCC FIFO. The length of the frame, including CRC bytes,
can be computed by subtracting this ending value from
the starting value of the RCLR. If RCLR is set to all ones, the
frame length is simply the ones complement of the ending
value.
S5. FIFO Thresholds
The Tx and Rx DMA thresholds must be set to at least 1 on
a 16-bit bus, meaning “request DMA transfer when at least
two characters have been received or when there are at
least two empty character locations in the TxFIFO”. Many
applications operate best if the DMA thresholds are set at
about half full. Lower values provide greater protection
against Rx Overruns and Tx Underruns, but can reach a
point of diminishing returns due to increasing overhead of
getting on and off the external bus.
It’s a good programming practice to protect the DMA
thresholds from inadvertent destruction by word writes to
the TICR and RICR, by writing “Select FIFO Status” com-
mands to the TCSR and RCSR after the thresholds are set.
Typically you don’t want Tx nor Rx Data interrupts in DMA
applications, in which case there’s no need to program the
Interrupt thresholds. Just leave the IE bits for these inter-
rupts 0.
S6. Interrupts for Rx Overrun and Tx Underrun
These are the two things the USC needs software to deal
with fairly immediately. Software should virtually always
enable interrupts for these two conditions. They are pref-
erable to related interrupts like Abort Sent because they
occur earlier and allow software to deal with the conditions
sooner.
UM009402-0201