Zilog Z16C30 User Manual

Page 74

5-7

Z16C30 USC

SER

ANUAL

ILOG

UM97USC0100

5.5.1 Enabling and Disabling the Receiver
and Transmitter

The

TxEnable

and

RxEnable

fields (TMR1-0 and RMR1-

0) enable and disable the Transmitter and Receiver to
send and receive serial data. 00 in TxEnable disables the
Transmitter, so that it keeps its output inactive and doesn’t
transfer characters from the TxFIFO to its shift register.
Assuming that the TxDMode field (IOCR7-6) is 00 to
propagate the Transmitter’s output onto TxD, the pin is a
constant Mark/high if the MSBit of the TxIdle field (TCSR10)
is 1 and/or the TxEncode field (TMR15-14) is 000 indicat-
ing NRZ data. If TxDMode is 00, TCSR10 is 0, and TxEncode
is non-zero, the TxD pin carries encoded ones.

If software changes TxEnable to 00 while the Transmitter is
sending a character, it discards the character and dis-
ables its output immediately. Similarly, 00 in RxEnable
disables the Receiver: it ignores the RxD pin and doesn’t
assemble characters. If software changes this field to 00
while the Receiver is assembling a character, it discards
the partial character.

01 in TxEnable or RxEnable disables the Transmitter or
Receiver in a more “graceful” way than 00. If software
changes TxEnable to 01 while the Transmitter is sending
asynchronous data, it finishes sending the current charac-
ter before going inactive. If software changes TxEnable to
01 while the Transmitter is sending synchronous data, it
finishes sending the current frame or message before
going inactive. If software changes RxEnable to 01 while
the Receiver is receiving asynchronous data, it finishes
assembling the current character before going inactive. If
software changes RxEnable to 01 while the Receiver is
receiving synchronous data, it finishes receiving the cur-
rent frame or message before going inactive.

10 in TxEnable or RxEnable enables the Transmitter or
Receiver unconditionally.

11 in TxEnable places the Transmitter under the control of
the /CTS pin. /CTS should be programmed as an input in
the CTSMode field of the Input/Output Control Register
(IOCR15-14). In this case, the Transmitter only starts
sending a character when /CTS is low. If /CTS goes high
while the Transmitter is sending a character in an async
mode, it finishes sending the character before going
inactive. In any synchronous mode, /CTS high summarily
disables the Transmitter. In either case, sooner or later,
/CTS high forces TxD to Mark or ones as described above
for TxEnable=00.

11 in RxEnable places the Receiver under the control of the
/DCD pin. /DCD should be programmed as an input in the
DCDMode field of the Input/Output Control Register
(IOCR13-12). The Receiver ignores the RxD pin and does
not assemble characters when /DCD is high. If /DCD goes
high while the Receiver is assembling a character in
External Sync mode or 802.3 (Ethernet) mode, it finishes
assembling the character and places it in the RxFIFO
before going inactive. In any other mode the Receiver
discards any partial character when /DCD goes high.

5.5.2 Character Length

The

TxLength

and

RxLength

fields (TMR4-2 and RMR4-

2) control how many bits the Transmitter sends and the
Receiver assembles in each character. The channel inter-
prets both fields as follows:

xMR4-2

Character Length

000

8 bits

001

1-bit

010

2 bits

011

3 bits

100

4 bits

101

5 bits

110

6 bits

111

7 bits

When TxLength specifies less than 8 bits, the Transmitter
discards/ignores one or more of the more-significant bits
of each byte that it takes from the TxFIFO.

When RxLength specifies less than 8 bits, the Receiver
replicates the most significant received bit in the more
significant bits of each byte it places in the RxFIFO. For
Async mode, it includes a received Parity bit, if any, in each
data byte. If RxLength, plus the Parity bit if any, is less than
8 bits, the Receiver fills out the more-significant bits of each
byte with the Stop bit, which is 1 except when there’s a
Framing Error.

UM009402-0201