Zilog Z16C30 User Manual

Page 93

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Z16C30 USC

SER

ANUAL

UM97USC0100

ILOG

5.18 STATUS REPORTING

The most important status reported by the Transmitter and
Receiver is available in the LSBytes of the Transmit and
Receive Command/Status Registers (TCSR and RCSR).
Figures 5-11 and 5-12 show the format of these registers.
It will be helpful to describe some common characteristics
of these status bits before discussing each individually.

When software writes and reads transmit and received
data directly to and from a serial controller, it can read and
write status and control registers as needed to handle the
overall communications process. But with the USC, exter-
nal DMA controllers often handle the data without software/
processor intervention. Because of this, software needs
other means of controlling the transmit and receive pro-
cesses and tracking their status. These means include the
Transmit and Receive Character Counters and the Trans-
mit Control Block and Receive Status Block features. Later
sections describe these features in considerable detail.
For now we just note that Receive Status Blocks allow the
Receive DMA controller to store a version of the RCSR in
memory with the received data. Such stored status differs
slightly from the status in the RCSR.

Software can program a channel to assert its Interrupt
Request output (/INTA or /INTB) based on certain bits in
the TCSR and RCSR. Chapter 7 covers interrupts in detail;
for now we’ll just note that a channel typically sets one of
these bits when a specified event occurs or a specified
condition starts. Such a bit typically remains 1 until host
software clears or “unlatches” it by writing a 1 to it. This
means that a channel won’t request another interrupt for
the same condition until software has written a 1 to the bit.
For the two interrupts that reflect the start of an ongoing
condition, IdleRcved and the “break” sense of Break/
Abort, the Receiver doesn’t clear the RCSR bit until the
software has written a 1 to unlatch the bit, and the condition
has ended.

Five of the bits in the RCSR (ShortF/CVType, RxBound,
CRCE/FE, Abort/PE, and RxOver) are associated with
particular received characters. The Receiver queues these
bits through the RxFIFO with the characters. The corre-
sponding bits in the RCSR may reflect the status of the
oldest character(s) in the FIFO, or that of the character last
read out of the FIFO, as described in the next few para-
graphs.

In order for these queued interrupt features to operate
properly, software should set the

WordStatus

bit in the

Receive Interrupt Control Register (RICR3) to 1 before it (or
the Rx DMA channel) reads data from the RxFIFO/RDR 16
bits at a time, and to 0 before it (or the RxDMA channel)
reads data 8 bits at a time.

Note that it’s essential for software to keep WordStatus in
the right state, when changing the IA bits in the LSbyte of
the RICR, or when writing DMA or interrupt threshold
values to the MSbyte.

The RxBound, Abort/PE, and RxOver bits actually operate
differently in the RCSR depending on whether software
has enabled each to act as a source of interrupts. If the
Interrupt Arm (IA) bit in the Receive Interrupt Control
Register (RICR) for one of these bits is 1, the channel sets
the RCSR bit to 1 when a character having the subject
status becomes the oldest one in the RxFIFO, or the
second-oldest with WordStatus=1. Once one of these bits
is 1, it stays that way until software writes a 1 to it. (The
channel doesn’t actually set the Receive Status IP bit to
request an interrupt for one of these bits, until software or
the Receive DMA controller reads the associated charac-
ter from RDR.)

For ShortF/CVType and CRCE/FE, and for RxBound, Abort/
PE, and RxOver when the associated IA bit is 0, if the last
time that software or an external Receive DMA controller
read this channel’s RxFIFO via the RDR, the channel
provided a character marked with RxBound status, then
these RCSR bits reflect the status of that character. This is
true only until software reads the (MSByte of the) RCSR, or
a Receive DMA controller stores it in the Receive Status
Block, or until software or the Receive DMA controller
reads RDR again.

For ShortF/CVType and CRCE/FE, and for RxBound,
Abort/PE, and RxOver when the associated IA bit is 0, if the
last time that software or the Receive DMA controller read
the RxFIFO via the RDR, the character returned (both of the
characters returned) had RxBound=0, or if software has
read the (MSByte of the) RCSR or the Receive DMA
controller has stored it in a Receive Status Block since the
last time either one read the RDR, then the RCSR bit
reflects the status of the oldest character(s) in the RxFIFO
(if any). In this latter case, if the RxFIFO is empty the status
bit is not defined. If the WordStatus bit is 1 in the Receive
Interrupt Control Register (RICR3) and there are two or
more characters in the FIFO, the status bit is the inclusive
OR of the status of the oldest two characters in the FIFO.
Otherwise the bit reflects the status of the oldest character
in the FIFO.

Just in case that wasn’t perfectly clear, the flowchart of
Figure 5-10 presents the same information.

UM009402-0201