Zilog Z16C30 - Manual (Page 137)

7-9
Z16C30 USC ®
U SER ' S M ANUAL Z ILOG
UM97USC0100
7.8 INTERRUPT OPTION IN THE BCR
One bit in the Bus Configuration Register (BCR) affects the
interrupt subsystem. This information is also presented in
Chapter 2, Bus Interfacing.
2PulseIACK (Double-Pulse Interrupt Acknowledge; BCR1):
software should program this bit to 0 if the /PITACK pin isn’t
used or if it carries a single pulse when the host processor
acknowledges an interrupt, or to 1 if /PITACK carries two
pulses when the host processor acknowledges an inter-
rupt. The latter mode is compatible with certain Intel
processors.
7.9 INTERRUPT ACKNOWLEDGE CYCLES
The USC doesn’t require Interrupt Acknowledge cycles.
The system designer can simply pull up the /SITACK and
/PITACK pins, and software can read the Interrupt Pending
(IP) bits in the Daisy Chain Control Register (DCCR), which
are described in later sections.
Even if the host processor does Interrupt Acknowledge
cycles, the USC doesn’t have to provide a vector. If IEI is
high and the NV bit in a channel’s Interrupt Control Register
(ICR) is 1, the channel sets the IUS bit of the highest priority
interrupt then pending, but it does not return an interrupt
vector.
But, since most microprocessors in use today perform
interrupt acknowledge cycles to obtain an 8-bit interrupt
vector, the rest of this section will assume vectored inter-
rupts.
Figure 7-5 shows an interrupt acknowledge cycle that’s
signalled by /SITACK, on a bus with multiplexed ad-
dresses and data. (Actually there are two subcases of this
kind of cycle, depending on whether the host processor
uses /DS or /RD signalling. Since the timing is the same for
either strobe, Figure 7-5 simply shows a trace labelled
“/DS or /RD”.)
If the channel samples /SITACK low at the rising edge of
/AS, it “freezes” its internal interrupt state; if it is requesting
an interrupt it forces its IEO output low regardless of the
state of IEI, and starts resolving its internal interrupt priori-
ties. If the IEI and IEO pins are part of an interrupt acknowl-
edge daisy chain with other interrupting devices, this
resolution occurs in concert with the interrupt logic in the
other devices.
The IEI pin must be valid for a specified setup time before
/DS or /RD goes low. The host CPU’s strobe must be
delayed if needed to guarantee this. If IEI is high and the
channel is requesting an interrupt, it responds to /DS or
/RD by setting the IUS bit of its highest requesting type of
interrupt, driving a vector onto the AD7-0 pins, and driving
/WAIT//RDY appropriately to signal when the vector is
valid. If IEI is low at the leading/falling edge of /DS or /RD,
and/or if the channel is not requesting an interrupt, it
doesn’t respond to the cycle.
UM009402-0201