Zilog Z16C30 - Manual (Page 160)

8-5
Z16C30 USC ®
U SER ' S M ANUAL Z ILOG
UM97USC0100
S7. Interrupt handling
A new section at the end of Chapter 7 gives specific
requirements for each type of interrupt. In general, the
strategy is 1) clear IP, 2) read the status bits, handle them
including clearing/unlatching them, and 3) clear IUS. Inter-
rupts can be lost if this order isn’t followed. The efficient-
sounding command “clear IP and IUS” that the USC offers,
is seldom a good idea and should be avoided, except
during device initialization.
S8. Clearing all IA bits for Rx and Tx Status
interrupts
For these two types of interrupts, software has to clear all
of the IA bits after it reads and clears the status bits, and
then set the desired IAs again, to ensure that any status
conditions that have arisen since software last read the
status, will cause a subsequent interrupt request.
S9. Priming the Transmitter for Transmit Control
Blocks
When using TCBs, after a hardware or software Reset,
software must force the Transmitter to expect the initial
TCB by issuing a Purge TxFIFO or Load TCC command.
S10. Interlocks are “after end of frame” not “before
start”
The three classes of interlocks for software synchroniza-
tion between frames, Wait2Send/Send Frame, Wait4TxTrig/
Trigger Tx DMA, and Wait4RxTrig/Trigger Rx DMA, all
occur after the end of a frame, not before the first frame
after the part is set up. Thus these three commands aren’t
needed after device initialization.
S11. Preserving loopback/echo settings
If you want to set a loopback or echo mode in CCAR9-8, be
sure to preserve it when writing commands to the MSbyte
of CCAR. If your processor has an “OR to memory”
command and the USC is memory-mapped, that instruc-
tion is a natural for issuing commands. Similarly, if your
application is on a 16-bit bus and must write indirect
register addresses to the CCAR, be sure to preserve
CCAR9-8 when doing so.
UM009402-0201