Zilog Z16C30 User Manual

Page 204

B-10

Z16C30 USC

SER

ANUAL

UM97USC0100

ILOG

DMA QUESTIONS AND ANSWERS

(Continued)

Since the Receive Status Block is appended to the end
of the data in memory, how does software determine
where the last byte of data is?

Rather than using a two word status block, use a one
word status block and then read the RCCR register for
the byte count of the frame. This register is FIFO’d four
deep to allow the system latency in reading out this
value. An alternative solution is to fill the memory buffer
with a known pattern when starting and find where the
pattern stops to determine how many bytes are in the
frame. The IUSC has a new feature that enables the
DMA to write the Receive Status Block as part of the
array table in array mode or as part of the linked-list in
linked-list mode.

The Technical Manual shows that /BUSREQ is driven
high 4.5 clocks after the rising edge of the strobe for
that last transfer. The specification is stated as a
minimum. What is the maximum?

The /BUSREQ signal drives high 4.5 clocks after the
strobe. This specification can be considered both a
min and max; the delay is always 4.5 clocks.

The IUSC AC specification #148 shows the maximum
active delay for the data bus after the rising edge of
clock. What is the minimum?

The minimum is 0 ns The IUSC can begin to drive the
address immediately after the rising edge of clock. A
delay of 15 ns would be typical.

Why does the IUSC insert inactive states after a bus
transfer without releasing bus control?

The ‘inactive’ states are used by the IUSC to update
the internal device status to determine if the bus
should be released. For example, after completely
filling the transmit FIFO, it is necessary to determine if
the receive channel needs to move data and, there-
fore, continue to hold mastership of the bus. Another
example of an ‘inactive state is the time between
fetching the link address pointer and the fetching the
link address in linked list mode.

Is there a signal that can be used as a ‘pre-warning’ of
the removal of the /BUSREQ signal? Is there a method
to reduce the number of clock cycles between the last
transfer to the deassertion of BUSREQ?

There is no signal to indicate the deassertion of
/BUSREQ. There is no known way to shorten the bus
release time. The 4.5 clocks to release the bus is a
small overhead to the total time for data transfers.

What is the advised sequence of register access to
initialize the DMA controller in the IUSC?

There is a chapter in the IUSC Technical Manual which
provides guidelines on the requirements for program-
ming sequence. Those used to the SCC will find the
IUSC much less sensitive to programming sequence.

What is the advised sequence of register access in
starting and continuing array chained DMA operation?
Are there any tricks to do this?

Once a DMA channel is initialized and enabled, con-
tinuous operation is automatic. It is recommended to
always maintain a link entry with a byte count of zero.
This will prevent the IUSC from accessing memory in
unexpected places if buffer processing falls too far
behind the serial data. The only trick to keeping the
DMAs going is for the memory management software
to keep ahead of the serial channel’s usage of memory
buffers.

In linked-list mode, what is the maximum number of
links in the chain?

There is no maximum number of buffers that can be in
the linked list. The size of the linked list is only limited
by the size of system memory and memory manage-
ment software.

In Linked List or Array mode, is there a method to
determine that a buffer has been started and com-
pleted?

The IUSC DMA channel can indicate that a buffer has
started use by enabling the Ring Buffer feature
(TDMR12 or RDMR12 set to 1). When the DMA channel
reads the buffer byte count, it will write back the count
value as zero. Therefore, software can check this word
to see that if the byte count is zero, the buffer count has
been read. Completion of the buffer can be easily
determined by enabling the Linked Status Transfer
feature (TDMR13 or RDMR13 set to 1). With this feature
enabled the Array and Linked List entries have an
unused word following the control/status words. This
unused word is written with zero’s when a buffer is
completed. Therefore, if this word is written with any
non-zero value when the array or list is set up, buffer
completion can be determined by checking this word.

UM009402-0201