Zilog Z16C30 - Manual (Page 200)

B-6
Z16C30 USC ®
U SER ' S M ANUAL
UM97USC0100
Z ILOG
SERIAL & PROTOCOL QUESTIONS AND ANSWERS (Continued)
Q: Is there a minimum length for HDLC/SDLC frames?
A: No, there is no minimum frame length. A frame can be
as short as: Opening Flag, 1 data character, CRC
(optional) and a Closing Flag. If address and control
field handling is specified, the receiver will post Short
Frame status in bit 8 of the RCSR if a closing flag is
received before the control field is complete.
Q: Is the rated serial data rate aggregate, or is the rated
speed for each receiver/transmitter?
A: Zilog specifies the maximum rated serial data rate for
each receiver/transmitter independently (not aggre-
gate).
Q: What is the maximum clock frequency for the Port 0 &
1 pins (IUSC only) when they are used as CLK0 &
CLK1 inputs?
A: The timing requirements for these inputs is the same
as for the /RxC pin.
Q: In HDLC mode, can the USC family do address search
and compare on a 16-bit address?
A: The USC family can check the first 8 bits of the address
field and receive or reject the frame if the incoming
address matches the programmed value (or the glo-
bal address of FFH).
Q: In HDLC mode, can the extended address/control
feature be used to check for a 16-bit address?
A: The extended address feature allows the device to
extend the point at which it begins to assemble data
according to the programmed character size. It doesn’t
extend the length of the address which is compared
for frame reception or rejection. Extending the ad-
dress/control field is useful when this field is in 8-bit
increments, but the data is in 7, 6, or 5 bit/char format.
Q: In HDLC mode, does an Abort set the End Of Frame
bit?
A: Yes, an Abort does set the End Of Frame status
(RCSR4), for the last data byte written to the receive
FIFO.
Q: In HDLC mode, does the receiver recognize shared
zero flags as well as non-shared zero flags? Will it
accept shared flags?
A: Yes, the receiver will recognize shared zero flags and
flags shared between frames.
Q: In HDLC mode, will the transmitter send one flag
between frames?
A: Yes, but only if data is present in the transmit FIFO
when the flag completes transmission. Otherwise an-
other flag or the idle line condition will be started. S26:
In 802.3 mode, is it required to end the frame by
deasserting /DCD?
Q: In 802.3 mode, it is required to end the frame by
deassering /DCD?
A: Yes, it is the deassertion of the /DCD pin that signals
the end of the message in 802.3 protocol. The 802.3
standard provides no other mechanism for terminat-
ing a frame. It’s part of the carrier sense in the descrip-
tion of CSMA/CD.
Q: In HDLC mode, is transmitting End Of Frame the same
as Underrun?
A: The End Of Frame (EOF) and Underrun are different
conditions in the USC family. There are register bits
that control the response for each condition sepa-
rately. This provides for automated response if the
transmitter underruns inadvertently before the intended
end of the frame. The transmitter reaches the Underrun
condition when there is no data to load into the transmit
shift register because the transmit data FIFO is empty.
What the transmitter does in this condition is pro-
grammed in the Channel Mode Register (CMR15-14).
The choices are to send either: an Abort (7 1’s), an
extended Abort (15 1’s), a Flag, or accumulated CRC
& Flag. The transmitter reaches the End Of Frame
condition when a byte marked with EOF status is
loaded into the transmit shift register. A byte can be
marked with EOF status in two ways: using the com-
mand “Set EOF/EOM” (TCSR15-12=1111), or when
the transmit character counter value reaches zero.
When the TxCRCatEnd bit in the TMR is set to one, the
byte marked with EOF status will be followed by CRC
and Flag.
Q: When the Receive Character Count (RCC) FIFO over-
flows (it is four entries deep), when is the RCC FIFO
overflow status bit (RCCF Ovflo) CCSR15 set?
A: The USC family sets the RCCF Ovflo bit is set in the
RCC FIFO for the fourth RCC FIFO entry when it
overwrites the previous fourth entry in the RCC FIFO.
The first three entries do not have the overflow status
set. Once the first three entries in the RCC FIFO are
read, the overflow bit will be set in the CCSR. The
overflow status is only cleared by writing a 1 to the
“Clear RCC FIFO” bit (CCSR13). This also empties the
RCC FIFO and clears the RCC FIFO Available bit.
UM009402-0201