Zilog Z16C30 User Manual

Page 55

4-6

Z16C30 USC

SER

ANUAL

UM97USC0100

ILOG

4.3.5 Clocking for Asynchronous Mode

For asynchronous reception, transitions on RxCLK don’t
have to have any relationship to transitions on RxD. When
the Receiver is searching for a start bit, it samples RxD in
each cycle of RxCLK, which it divides by 16, 32, or 64 to
determine the bit rate. After the Receiver finds the 1-to-0
transition at the beginning of each start bit, it counts off the
appropriate number of RxCLK cycles to the middle of the
bit cell (8, 16, or 32). At this point it samples RxD to validate
the start bit. If RxD has gone back to 1, the Receiver
ignores the prior transition as line noise and goes back to
searching for a start bit. If RxD is still 0, the Receiver
accepts the start bit. Then it counts off 16, 32, or 64 RxCLK
cycles to the middle of each subsequent bit of the charac-
ter, and samples RxD at those times.

For asynchronous transmission, if a Transmitter has been
idle and software then provides it with data and enables it,
it drives TxD from 1 to 0 for the Start bit at the falling edge
on TxCLK that follows the latter of these two steps. It
applies each subsequent bit to TxD after counting off 16,
32, or 64 TxCLK cycles. When sending successive async
characters, the Transmitter waits for the stop bit length
programmed in the two MSBits of the TxSubMode field of
the Channel Mode Register (CMR15-14), before driving
TxD from 1 to 0 for a subsequent start bit. If these bits
specify “shaved” operation, the Transmitter adjusts the
stop bit length per the TxShaveL field of the Channel
Control Register (CCR11-8).

4.3.6 Synchronous Clocking

Except in asynchronous operation, one cycle on RxCLK
corresponds to one data bit on RxD, and one TxCLK cycle
corresponds to one bit on TxD. In any of the synchronous
modes, the clock used by the receiver to sample the data
must be similar to the one used by the remote transmitter
to send the data.

The simplest way to ensure this is to use a separate wire to
send the clock from one station’s transmitter to the other
station’s receiver. But often cost or the nature of the serial
medium prevents this — for example, you can’t send a
separate clock over a telephone line. In such cases it is

common practise to encode the data so that serial stream
also includes clocking information. For such applications,
the USC can encode transmitted data and decode re-
ceived data in any of several popular formats.

In addition, each channel’s Digital Phase Locked Loop
(DPLL) module can recover a synchronized RxCLK from
the received data. While the DPLL can source TxCLK as
well, such operation propagates some of the clock jitter
from this station’s receive path onto its transmit path, which
may increase the error rate.

4.3.7 Stopping the Clocks

CMOS circuits like those in the USC don’t draw much
power compared to older technologies, but their power
requirements can be reduced still further if their clock
signals are stopped when the circuits don’t need to oper-
ate. Most of this power savings can be obtained by having
the software disable RxCLK and TxCLK by writing zeroes
to the RxCLKSrc and TxCLKSrc fields (CMCR2-0 and
CMCR5-3). If the Counters and Baud Rate Generators are
used, power consumption is reduced further if software
disables them by writing zeroes to as many as possible
among CTR0Src, CTR1Src, BRG0Src, and BRG1Src
(CMCR13-12, CMCR15-14, CMCR9-8, and CMCR11-10).
The ultimate in power savings is obtained by having
external logic stop the input clock(s) on the /RxC and/or
/TxC pins.

When RxCLK is stopped, previously-received data can be
read from the RxFIFO, but RxD is ignored so that no further
data will arrive. A final character will be available to the
software and/or the Receive DMA controller if RxCLK runs
for at least three cycles after its last bit is sampled from
RxD. For HDLC/SDLC this means at least 3 RxCLKs after
the receiver samples the last bit of a closing Flag. For
Async it means at least 3 RxCLKs after the receiver
samples the stop bit of the last character.

TxCLK can be stopped after the last desired bit has gone
out on TxD. This is 2 or 3 TxCLKs after the last bit has left
the Transmit shift register (because of the Transmit encod-
ing logic), which in turn occurs 1 or 2 TxCLKs after the
Transmitter sets the TxUnder bit (TCSR1).

UM009402-0201