Zilog Z16C30 User Manual

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Z16C30 USC

SER

ANUAL

ILOG

UM97USC0100

5.22 THE DATA REGISTERS AND THE FIFOS

When the RxFIFO contains received characters, software
can read the “oldest” 1 or 2 characters in it from the
Received Data Register (RDR). When software uses an
external Receive DMA controller, the DMA controller takes
care of taking data out of the RxFIFO. 'The Mode Registers:
Character Length', earlier in this Chapter, describes how
the Receiver aligns characters and fills out bytes in the
RDR/RxFIFO when characters are less than 8 bits long.

Similarly, when the TxFIFO isn’t full software can write 1 or
2 characters to the Transmit Data Register (TDR), or an
external DMA controller can do so.

5.22.1 Accessing the TDR and RDR

Chapter 2 describes how software can access the TDR
and RDR using a register address that may be 1) multi-
plexed on the AD6-0 pins, 2) full-time on AD13-8 if only
AD7-0 carry data, or 3) written into the Channel Command/
Address Register (CCAR6-0).

Two other features of the USC make it easier for software
to access these registers when the AD lines don’t carry
multiplexed addresses and the data bus is 16 bits wide.
Host processor write cycles to the USC, with the D//C pin
high, always write the TDR. Similarly, host processor read
cycles from the USC, with D//C high, always read the RDR.
A system designer may connect D//C to a processor
address line, such as A1 for a non-multiplexed 16-bit bus
or A7 for a multiplexed bus.

Chapter 2 also describes how to write the Bus Configura-
tion Register to configure the USC for a 16-bit data bus.
With a 16-bit data bus, software can write two characters
at once to the TDR, or an external Transmit DMA controller
can read two characters from memory at once. Similarly,
software can read two characters at a time from the RDR,
or an external Receive DMA controller can write two
characters into memory in each bus cycle. The earlier
section 'Commands' describes how the “Select D15-8
First” and “Select D7-0 First” commands allow the two
characters in each 16-bit transfer, to the TDR or from the
RDR, to be arranged in either order. This is important
because available microprocessors differ about the order.

With a 16-bit data bus, software can read or write most
USC registers as a 16-bit word, or can read or write either
their “more significant” byte (bits 15-8) or “less significant”
byte (bits 7-0). The TDR and RDR are different in this
regard: software should never read or write their more
significant bytes alone, only as part of a 16-bit transfer. On
a Zilog Z8000 or 16C0x or Motorola 680x0 based system
this means that software should write bytes to the TDR and
read bytes from the RDR at an odd address. On a Zilog
Z380

™

or Intel 80x86 processor, software should write

bytes to the TDR and read bytes from the RDR at an even
address.

On a 16-bit bus there’s no way for software to read single
characters from the RDR, or write single characters to the
TDR, using an address that makes D//C high. To do this,
software must either address the LSByte of the TDR/RDR
directly, or it must write the address of the LSByte to the
CCAR.

5.22.2 TxFIFO and RxFIFO Operation

The TxFIFO and RxFIFO have a maximum capacity of 32
characters (bytes) each. A USC channel empties them of
all data when external hardware drives the /RESET pin low,
when software resets the channel via the RTReset bit
(CCAR10), and when software writes a "Purge Rx" or
“Purge Rx' and/or Tx FIFO” command to the RTCmd field
(CCAR15-11).

The RxFIFO becomes one byte more full for each charac-
ter received on the serial link, and one or two bytes less full
each time software or an external Receive DMA controller
reads data from it via the RDR. The TxFIFO becomes one
or two bytes more full each time software or an external
Transmit DMA controller writes data to the TDR, and one
byte less full each time the Transmitter moves a character
into its output shift register.

One further point about RxFIFO operation applies only in
HDLC/SDLC, HDLC/SDLC Loop, 802.3, and Transparent
Bisync. In one of these modes, if software or the Rx DMA
channel reads 16 bits from the RDR when the oldest
character in the RxFIFO is the last one of a frame (i.e., it’s
marked with RxBound status), the USC channel removes
only that one character from the RxFIFO.

UM009402-0201