Zilog Z16C30 - Manual (Page 54)

4-5
Z16C30 USC ®
U SER ' S M ANUAL Z ILOG
UM97USC0100
The output of either Baud Rate Generator can be used as
RxCLK and/or TxCLK. It can be used as the reference
clock input to the Digital Phase Locked Loop (DPLL)
circuit, and it can be output on the /RxC or /TxC pin.
When a Baud Rate Generator isn’t used to make a serial
clock, software can use it for other purposes such as
protocol timeouts, and can program the channel to request
an interrupt when it counts down to zero. Chapter 6 covers
interrupts in detail, but to use BRG interrupts software
should write 1’s to the BRG1 IA bit and/or BRG0 IA bit in the
Status Interrupt Control Register (SICR1 and/or SICR0), as
well as to the MIE and Misc IE bits in the Interrupt Control
Register (ICR15 and ICR0).
4.3.3 Introduction to the DPLL
There is one Digital Phase Locked Loop (DPLL) circuit in
each channel of a USC; it represents the “third stage” of the
channel’s clock-generation logic. The DPLL is a 5-bit
counter with control logic that monitors the serial data on
RxD. The
DPLLSrc field of the Clock Mode Control Regis-
ter (CMCR7-6) controls which signal the DPLL uses as its
nominal or reference clock:
DPLLSrc DPLL Reference Clock
00 BRG0 output
01 BRG1 output
10 /RxC pin
11 /TxC pin
The DPLLDiv field of the Hardware Configuration Register
(HCR11-10) determines whether the DPLL divides this
reference clock by 8, 16, or 32 to arrive at its nominal bit
rate, as follows:
DPLLDiv Nominal DPLL Clock
00 reference clock/32
01 reference clock/16
10 reference clock/8
11 Reserved (/4 for CTR1)
The 11 value cannot be used for DPLL operation, but if the
DPLL isn’t used, software can program this value, together
with a 1 in the CTR1DSel bit (HCR13), to operate CTR1 in
“divide by four” mode.
A later section describes the operation of the DPLL in
greater detail, but for now it’s sufficient to note that it
samples the (typically encoded) data stream on RxD to
produce separate receive and transmit outputs. These
outputs are synchronized to the bit boundaries on RxD,
and can be used as RxCLK and/or TxCLK and/or can be
routed to the /RxC or /TxC pin.
4.3.4 TxCLK and RxCLK Selection
The Transmitter can take its TxCLK from any of the sources
described in preceding sections, under control of the
TxCLKSrc field of the Clock Mode Control Register
(CMCR5-3):
TxCLKSrc Source of TxCLK
000 No clock (xmitter disabled)
001 /RxC pin
010 /TxC pin
011 Tx output of DPLL
100 BRG0 output
101 BRG1 output
110 CTR0 output
111 CTR1 output
Similarly, the Receiver can take its RxCLK from various
sources, under control of the
RxCLKSrc field of the Clock
Mode Control Register (CMCR2-0):
RxCLKSrc Source of RxCLK
000 No clock (receiver disabled)
001 /RxC pin
010 /TxC pin
011 Rx output of DPLL
100 BRG0 output
101 BRG1 output
110 CTR0 output
111 CTR1 output
UM009402-0201