Zilog Z16C30 - Manual (Page 144)

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Z16C30 USC ®
U SER ' S M ANUAL
UM97USC0100
Z ILOG
7.11.2 Receive Data Interrupts (Continued)
To program the Receive Data Interrupt Request Level, first
write the “Select RICRHi=/INT Level” command to the
RCmd field of the Receive Command/Status Register
(RCSR15-12). Then write the number of received charac-
ters at which the channel should start requesting a Receive
Data interrupt, minus one, to the MSByte of the Receive
Interrupt Control Register (RICR). For example, if the
channel should request a Receive Data interrupt when its
32-byte RxFIFO becomes 3/4 full, write hex 60 to RCSR15-
8, then write decimal 23 (hex 17) to RICR15-8.
It is good programming practice to follow these two steps
with writing a “Select RICRHi=FIFO Status” command to
the RCSR, to protect the Request Level from inadvertent
modification when other parts of the software change the
IA bits in the RICR.
Code that writes or reads the Receive Data Interrupt
Request threshold must ensure that no interrupts will occur
between the time it writes the “Select RICRHi=/INT Level”
command to the RCSR, and when it writes or reads the
value in the RICR, if such interrupts can lead to other code
writing a different Select command (for the FIFO Fill level
or DMA request threshold) to the RCSR.
Figure 7-11 shows a sample service routine for Receive
Data interrupts. While it’s not particularly fancy or efficient,
it does illustrate several important points:
1. It reads the FIFO fill level to determine how many
characters to read. The fact, that reception of an
RxBound character (i.e., the last character of a frame,
message, can set the Receive Data IP bit, means that
a Receive Data interrupt service routine can’t blindly
read the number of characters implied by the Interrupt
Request Level.
2. It explicitly clears the Receive Data IP and IUS bits by
writing to the Daisy Chain Control Register (DCCR) as
described in a later section. Neither bit is affected by
reading data from the RxFIFO.
3. It re-reads the FIFO fill level after clearing the IP bit, and
processes any characters that have been received
while it was processing earlier characters. This proce-
dure guards against losing an interrupt associated
with a late-arriving End of Frame (RxBound) character.
4. It reads the status from RCSR “before” reading each
character, and reads RCSR an extra time after reading
out an End of Frame (RxBound) character, to clear the
latching of the status that occurs when an RxBound
character is read out.
(This is not the only way to handle RxBound checking.
Another way is to enable a Receive Status interrupt when
the Receive Data interrupt service routine reads a RxBound
character out of the RxFIFO, and not check RxBound
status in this routine at all. Software that uses this method
must ensure that an Receive Status interrupt can interrupt
the Receive Data ISR in a “nested” fashion.)
UM009402-0201