Zilog Z16C30 - Manual (Page 142)

7-14
Z16C30 USC ®
U SER ' S M ANUAL
UM97USC0100
Z ILOG
7.10 INTERRUPT ACKNOWLEDGE VS. READ CYCLES
Interrupt Acknowledge cycles are similar to the cycles that
occur when the host processor reads a USC register,
which are discussed in Chapter 2. However, the user
should note the following ways in which interrupt acknowl-
edge cycles differ from read cycles:
■ On a multiplexed bus, /SITACK acts like an address
line. When a USC samples /SITACK low at a rising
edge on /AS, it ignores the address on the AD lines.
■ On a non-multiplexed bus, each leading edge of /RD
or /DS captures the state of /SITACK.
■ With /DS signalling, the state of R//W doesn’t matter for
a cycle in which the USC samples /SITACK low. (In
other cycles R//W differentiates Read cycles from
Writes.)
■ When the /WAIT//RDY pin carries the Wait function, a
USC channel asserts the pin during interrupt
acknowledge cycles, but never does so during register
Read or Write cycles.
■ When /WAIT//RDY carries the Acknowledge function,
a channel asserts it later in Interrupt Acknowledge
cycles than in Reads. However, the relationship
between the falling edge of /WAIT //RDY and the
validity of data on the AD lines is similar in both kinds
of cycles.
7.11 INTERRUPT TYPES
Each USC channel includes six types of interrupts, ar-
ranged on the internal interrupt daisy chain in the following
priority order:
1. Receive Status (highest priority)
2. Receive Data
3. Transmit Status
4. Transmit Data
5. I/O Pin
6. Miscellaneous (lowest priority)
Each of these types has one each IE, IP, and IUS bit, as
described in an earlier section of this chapter.
7.11.1 Receive Status Interrupt Sources
and IA Bits
Any of six interrupt sources can set a channel’s Receive
Status IP bit. Software can read the status of each source
in the LSByte of the Receive Command/Status Register
(RCSR), which is shown in Figure 7-9. The following de-
scriptions of the RCSR status bits are similar to those in the
'Detailed Status in the RCSR' section of Chapter 4:
ExitedHunt The RS IP bit can be set when this bit
(RCSR7) goes from 0 to 1 because the
receiver has detected a Sync or Flag
sequence in a synchronous mode.
IdleRcved The RS IP bit can be set when this bit
(RCSR6) goes from 0 to 1 because the
receiver has seen 15 or 16 consecutive
one bits. In asynchronous modes with 16,
32, or 64x clocking, the receiver sets
RCSR6 after one bit time or less, so this
source’s IA bit shouldn’t be set in such
modes.
Break/Abort The RS IP bit can be set when this bit
(RCSR5) goes from 0 to 1 because the
Receiver has detected a Break condition
in an asynchronous mode or an Abort
condition in HDLC/SDLC mode.
RxBound If the IA bit for this source is 1, the interrupt
logic sets the RS IP bit when software or
the Receive DMA channel reads a char-
acter from the RxFIFO that’s marked with
RxBound status. Such marking reflects an
address character in Nine-Bit mode, ne-
gation of /DCD during the character in
external sync mode, the last character of
a frame in HDLC/SDLC and 802.3 modes,
or one of five block terminating characters
in Transparent Bisync mode.
UM009402-0201