Zilog Z16C30 User Manual

Page 98

5-31

Z16C30 USC

SER

ANUAL

ILOG

UM97USC0100

RxOver:

The Receiver queues this bit through the RxFIFO

with each received character. It sets the bit to indicate a
Receive FIFO overrun, but the overrun isn’t visible to
software until the character that caused it is the oldest one
in the RxFIFO, or the second-oldest with WordStatus=1.

As described earlier in this Status Reporting section,
RCSR1 may represent an interrupt bit, or the status at the
time a RxBound character was read from the RxFIFO, or
the status associated with the oldest 1 or 2 character(s) still
in the RxFIFO. In a stored Receive Status Block this bit may
represent an interrupt bit or the status of the previous
character.

The Receiver sets this bit to 1 for the first character for
which there was no room, which is held in a holding register
between the shifter and the RxFIFO. Once this happens,
the Receiver doesn’t store any more received characters
in the RxFIFO, until software responds as described in
‘Handling Overruns and Underruns’ later in this chapter.

A channel can request an interrupt when software or a
DMA channel reads a character from the RDR that has this
bit set, if the RxOver IA bit in the Receive Interrupt Control
Register (RICR1) is 1. In this case, software must write a 1
to RxOver to unlatch it and allow further interrupts; writing
a 0 has no effect.

RxAvail:

This read-only bit (RCSR0) is 1 if the RxFIFO

contains 1 or more characters, or 0 if it’s empty.

5.19 DMA SUPPORT FEATURES

When software writes and reads all the data to and from a
serial controller, it can maintain its own counters and
length-tracking mechanisms, and can use them to tell
when to read status and issue commands. But in DMA
applications we would like to “decouple” the processor
and its software from such intimate and real-time involve-
ment with the transmit and receive processes. This is only
possible if we include features in the serial and/or DMA
controllers, by which software can figure out the length and
correctness of frames or messages long after they’re
received, and by which the hardware can change param-
eters and save status information at appropriate points
with as little processor software involvement as possible.

The USC features that support such operation include the
Receive and Transmit Character Counters, the RCC FIFO
that stores the length of received frames, the Transmit
Control Block feature that allows software to include con-
trol information with transmit data in Transmit DMA buffers,
and the Receive Status Block feature that stores status with
received data in Receive DMA buffers. The following
subsections describe these features.

5.19.1 The Character Counters

The Transmitter includes a 16-bit Transmit Character
Counter (TCC) that software can use to control the length
of transmitted frames and messages in DMA applications.
The Receiver includes a similar Receive Character Counter
(RCC) that software can use to record and save the length
of frames and messages in DMA applications. Software
can also use the RCC to cause an interrupt if a frame
exceeds a certain length.

While most of this section describes these features in
terms of the length of frames and messages in synchro-
nous protocols, they may be useful in asynchronous work
as well.

Figures 5-13 and 5-14 show the structure of the TCC and
RCC features, respectively. Software can write the 16-bit
Transmit Count Limit Register (TCLR) at any time, to define
the length of the next transmitted message(s) or frame(s).
Similarly, it can write the 16-bit Receive Count Limit Reg-
ister (RCLR) at any time, to define the length of future
received messages and frames at which the Receiver will
interrupt. Software can also use the Transmit Control Block
feature to make a channel automatically fetch a new value
for the TCLR and TCC from memory before each block of
characters. The TCLR and RCLR can be read back at any
time. A channel never changes their values except to clear
them to zero at reset time, and when it loads TCLR from a
32-bit Transmit Control Block.

Writing the TCLR or RCLR doesn’t have any immediate
effect on the TCC or RCC feature. Only when one of several
events occurs does a channel load the value from TCLR or
RCLR into the actual 16-bit character counter. If the value
in TCLR or RCLR is zero at that time, the channel disables
the TCC or RCC feature, while if the value is nonzero it
enables the feature.

UM009402-0201