Zilog Z16C30 - Manual (Page 148)

7-20
Z16C30 USC ®
U SER ' S M ANUAL
UM97USC0100
Z ILOG
7.11.5 I/O Pin Interrupt Sources and IA Bits
The interrupt logic can set the I/O Pin IP bit in response to
rising and/or falling edges on any of six pins for each
channel, namely /RxC, /TxC, /RxREQ, /TxREQ, /DCD, and
/CTS. The following description is similar to that in the
'Edge Detection and Interrupts' section of Chapter 4.
Software can program the channel to detect rising and/or
falling edges on the /CTS, /DCD, /TxC, /RxC, /TxREQ, and
/RxREQ pins, and to interrupt when such events occur.
Figure 7-14 shows that the Status Interrupt Control Regis-
ter (SICR) includes separate Interrupt Arm (IA) bits for
rising and falling edges on each of these pins. A 1 in one
of these bits makes the channel detect that kind of edge,
while a 0 makes it ignore such edges. This edge detection
and interrupt mechanism operates without regard for
whether the various pins are programmed as inputs or
outputs in the I/O Control Register (IOCR).
When a channel detects an edge that’s enabled in the
SICR, it records the event in an internal latch that’s not
directly accessible in the USC’s register map. Instead, as
shown in Figure 7-15, the Miscellaneous Interrupt Status
Register (MISR) includes two bits for each of these six pins,
one called a “Latched/Unlatch” or L/U bit, and the other
being a “data bit” that has the same name as the pin itself.
A hardware or software Reset sequence clears all the L/U
bits to zero. While the L/U bit for a pin is 0, the associated
data bit reports and tracks the state of the pin in a
“transparent” fashion, with a 1 indicating a low and a 0
indicating a high.
Whenever a pin’s L/U bit is 0 and its internal edge-
detecting latch is set, the channel sets the L/U bit to 1,
clears the detection latch, and sets the IOP IP bit. IOP IP
can be read and cleared (and if necessary set) in the Daisy
Chain Control Register (DCCR1).
While an L/U bit is 1, the state of the associated data bit is
frozen (latched). These two bits remain in this state, re-
gardless of further transitions on the pin, until software
writes a 1 to the L/U bit. This clears the L/U bit to 0 and
“opens” the data bit to once again report and track the
state of the pin, at least for an “instant”. If one or more
enabled transitions occurred while the L/U bit was set, then
L/U is set again right after software writes the 1 to it.
Writing a 0 to an L/U bit has no effect; it doesn’t matter what
value software writes in the “data” bits.
7.11.6 Miscellaneous Interrupt Sources and
IA Bits
The interrupt logic can set the Miscellaneous IP bit in
response to any of four interrupt sources. Software can
read the status of these sources in the LSByte of the
Miscellaneous Interrupt Status Register (MISR), which is
shown in Figure 7-15. The following descriptions repeat
some information that was presented in Chapters 4 and 5:
RCCUnder If the RCCUnder IA bit is 1, a channel
sets this bit (MISR3) and the Misc IP bit
if the receiver has decremented the
Receive Character Counter (RCC) to
zero and then it receives another char-
acter (in the same frame/message).
DPLLDSync If the DPLLDSync IA bit is 1, a channel
sets this bit (MISR2) and the Misc IP bit
if software set up the Digital Phase
Locked Loop circuit for Biphase en-
coding and the DPLL detects two con-
secutive missing clocks, indicating a
loss of synchronization.
BRG1 If the BRG1 IA bit is 1, a channel sets
this bit (MISR1) and the Misc IP bit
when Baud Rate Generator 1 counts
down to zero.
BRG0 If the BRG0 IA bit is 1, a channel sets
this bit (MISR0) and the Misc IP bit
when Baud Rate Generator 0 counts
down to zero.
Once any of these bits is 1, software must write a 1 to that
bit position to “unlatch” it. Writing a 1 to any of MISR3-0
clears the “read-side” bit unless the setting event recurred
while the bit was latched, in which case the bit is set again
immediately.
Each of these four sources has a separate Interrupt Arm
(IA) bit in the LSByte of the Status Interrupt Control Register
(SICR). Figure 7-14 shows the SICR. If an IA bit is 1, the
interrupt logic sets the corresponding bit in MISR, and the
Miscellaneous IP bit, when the indicated condition occurs.
If an IA bit is 0, the logic won’t set the corresponding MISR
bit and thus the associated condition can’t cause inter-
rupts. Clearing an IA bit does not clear the corresponding
bit in MISR.
UM009402-0201