Zilog Z16C30 - Manual (Page 10)

Z16C30 USC ®
U SER ' S M ANUAL
vi
Z
ILOG
UM97USC0100
F
IGURE
T
ITLES
P
AGE
Chapter 1
Figure 1-1. USC Logic Symbol ................................................................................. 1-2
Figure 1-2. USC 68-pin PLCC Pinout ........................................................................ 1-3
Figure 1-3. USC Block Diagram .............................................................................. 1-11
Chapter 2
Figure 2-1. Simple Multiplexed System .................................................................... 2-1
Figure 2-2. Simple Interface to Non-Multiplexed Bus ............................................... 2-2
Figure 2-3. User-Friendly Interface to Non-Multiplexed Bus .................................... 2-2
Figure 2-4. /RD & /WR Signaling ............................................................................... 2-3
Figure 2-5. R//W and /DS Signaling .......................................................................... 2-3
Figure 2-6. A Fast and Slow Cycle with Three Kinds of Handshaking ..................... 2-5
Figure 2-7. The USC's Bus Configuration Register (BCR) ........................................ 2-7
Figure 2-8. The Channel Command/Address Register (CCAR) ............................. 2-10
Figure 2-9. USC Register Addressing .................................................................... 2-11
Figure 2-10. A Register Read Cycle with Multiplexed Addresses and Data ............ 2-15
Figure 2-11. A Register Write Cycle with Multiplexed Addresses and Data ............ 2-16
Figure 2-12. A Register Read Cycle with Non-Multiplexed Data Lines .................... 2-17
Figure 2-13. A Register Write Cycle with Non-Multiplexed Data Lines ..................... 2-18
Chapter 3
Figure 3-1. Sample Application ................................................................................ 3-2
Figure 3-2. Serial Interface for Sample Application .................................................. 3-3
Chapter 4
Figure 4-1. A Model of a USC Channel's Clocking Logic ......................................... 4-3
Figure 4-2. The Clock Mode Control Register (CMCR) ............................................ 4-4
Figure 4-3. The Hardware Configuration Register (HCR) ......................................... 4-4
Figure 4-4. Data Formats/Encoding .......................................................................... 4-7
Figure 4-5. The Channel Command/Status Register (CCSR) ................................... 4-9
Figure 4-6. The Input/Output Control Register (IOCR) ........................................... 4-10
Figure 4-7. The Status Interrupt Control Register (SICR) ........................................ 4-12
Figure 4-8. The Miscellaneous Interrupt Status Register (MISR) ............................ 4-12
Figure 4-9. /DCD Auto-Enable Timing .................................................................... 4-14
Figure 4-10. /CTS Auto-Enable Timing ..................................................................... 4-15
UM009402-0201