Zilog Z16C30 - Manual (Page 126)

6-7
Z16C30 USC ®
U SER ' S M ANUAL Z
ILOG
UM97USC0100
“Forcing out a frame” in D1. above applies only in HDLC/
SDLC, HDLC/SDLC Loop, 802.3, or Transparent Bisync,
and operates differently on USCs manufactured before or
after June 1993.
On the older devices, the Receiver set a state that forced
/RxREQ to be asserted when the end of a frame was
received, and cleared this state whenever the Rx DMA
controller read out the last character of a frame. Newer
devices operate similarly when no Receive Status Blocks
or 16-bt RSBs are enabled, except that they also clear the
state when the Rx DMA channel reads out a character with
Overrun status. (The latter avoids a problem called “scrib-
bling” wherein the Receiver kept requesting DMA transfer
constantly if the end of a frame arrived while the Receiver
was Overrun.)
When 32-bit RSBs are enabled, USCs manufactured after
June 1993 assert /RxREQ whenever the RCC FIFO is not
empty, that is, when the RCCFAvail bit (CCSR14) is 1.
Since these devices take the second word of a 32-bit RSB
from the RCC FIFO, this approach represents a frame-
forcing mechanism that operates optimally even when
more than one end-of-frame character is in the RxFIFO at
the same time.
Regardless of the age of the device, it maintains an EOF-
forcing /RxREQ until the Rx DMA channel reads out a
completed Receive Status Block if RSBs are enabled, or
else until it reads out the last received character of a frame
(which is typically part of a CRC).
“Waiting for a Trigger Command” (in item C. above) occurs
only when the Wait4RxTrig bit in the Channel Control
Register (CCR5) is 1 in HDLC/SDLC, HDLC/SDLC Loop,
802.3, or Transparent Bisync. In this case, after the Rx
DMA channel reads out the end of a message or frame
including the RSB if any (thus clearing the EOF-forcing
state of D1. above), the Receiver negates /RxREQ and
doesn’t assert it again until software writes a “Trigger Rx
DMA” command to the RTCmd field of the Channel Com-
mand/Address Register (CCAR15-11). This interlock can
be used to read the length of the frame from the Rx DMA
channel, and/or to reprogram the Rx DMA channel for the
next frame. This interlock overrides points A and B above.
The Receive Character Counter feature cannot force the
Receiver to assert /RxREQ.
A channel negates /TxREQ within a specified time of the
start of the bus cycle that fills the TxFIFO or fetches the last
character of the frame or message. A channel negates
/RxREQ within a specified time after the start of a bus cycle
that empties the RxFIFO or completes the storing of the
Receive Status Block.
6.3.1 Programming the DMA Request
Levels
As noted in other chapters, the MSByte of the Transmit and
Receive Interrupt Control Registers (TICR and RICR) may
each represent any of several registers. The content of
each register’s MSByte depends on which of several
selection commands was most recently written to the
Transmit or Receive Command Status Register (TCSR or
RCSR), respectively. The selections for the Transmitter
and Receiver are independent.
To program or read back a DMA Request Level, first write
the “Select RICRHi=/RxREQ Level” or “Select TICRHi=
/TxREQ Level” command (both being the value 0111) to
the TCmd or RCmd field of the Transmit or Receive
Command/Status Register (TCSR15-12 or RCSR15-12).
This step can be omitted if it’s known that no 0101 or 0110
commands have been written to TCSR or RCSR since the
last time 0111 was written there. The DMA Request Level
value can then be read or written as the MSByte of the TICR
or RICR.
The Transmit DMA Request Level should be programmed
with 1 less than the number of empty TxFIFO positions, at
which the Transmitter should start asserting /TxREQ. The
Receive DMA Request Level should be programmed with
1 less than the number of received characters in the
RxFIFO, at which the Receiver should start asserting
/RxREQ. For example, if the Receiver should request DMA
operation when its 32-byte RxFIFO is 3/4 full, software
should write hex 70 to RCSR15-8 to select the DMA
Request Level as RICR15-8, and then write decimal 23
(hex 17) to RICR15-8.
Both DMA Request Levels must be programmed to at
lease 1 when using 16-bit DMA transfers.
It is good programming practice to follow the writing of
Request Level(s) with writing a “Select RICRHi=FIFO Sta-
tus” command to the RCSR, and/or a “Select TICRHi=FIFO
Status” command to the TCSR as applicable, to protect the
Request Level(s) from inadvertent modification when other
parts of the software change the IA bits in the LS byte of the
RICR or TICR.
UM009402-0201