Zilog Z16C30 - Manual (Page 78)

5-11
Z16C30 USC ®
U SER ' S M ANUAL Z ILOG
UM97USC0100
5.8 NINE-BIT MODE
This mode is compatible with various equipment including
some Intel single-chip microcontrollers. In some contexts
it’s called “address wakeup mode”. Software can select it
for the Transmitter and the Receiver by programming the
TxMode and RxMode fields (CMR11-8 and CMR3-0 re-
spectively) to 1000. Operation on the line is similar to
Async mode, using a single stop bit and either eight data
bits or seven data bits plus a parity bit. Following the eighth
(MS) data bit or the Parity bit, an additional bit differentiates
normal data characters from “destination address” char-
acters. Address characters identify which of several sta-
tions on the link should receive the following data charac-
ters. In effect, Nine Bit mode is like a Local Area Network
using asynchronous hardware.
The Transmitter saves TxSubMode bit 3 (CMR15) with
each character as it goes into the TxFIFO, and sends this
bit as that character’s address/data bit. By convention a 0
signifies “data” and a 1 signifies “address”. As software or
an external Transmit DMA controller writes each character
into the TxFIFO, the channel saves the state of CMR15 with
it. This bit accompanies the character through the FIFO
and out onto the link.
TxSubMode bit 2 (CMR14) selects between eight data bits
or seven data bits plus parity:
CMR14 Data bits
0 Eight
1 Seven plus parity
The TxParEnab bit in the Transmit Mode Register (TMR5)
must be set to the same value as this bit.
Typically, Nine Bit receivers check the parity of received
address bytes. This means that when software selects
eight data bits, it must calculate its own parity bit in the MSB
of addresses.
RxSubMode bit 2 (CMR6) similarly controls parity check-
ing of characters marked as Data, thus allowing 8-bit data,
while a 1 enables parity checking, thus limiting data
characters to 7 data bits. The Receiver always checks the
parity of address bytes. The RxParEnab bit in the Receive
Mode register (RMR5) must be set to the same value as this
bit.
As in Async mode, the two LSbits of the Tx and RxSubMode
fields (CMR13-12 and CMR5-4) control whether the Trans-
mitter and Receiver divide their TxCLK and RxCLK inputs
by 16X, 32X, or 64x to arrive at the nominal bit length. See
the preceding Async section for the field encodings and a
discussion of the significance of this choice.
The Receiver sets the RxBound status bit for a received
address character, that is, a character that has its ninth bit
set to 1. This bit accompanies the character through the
RxFIFO and ends up in the Receive Command/Status
Register (RCSR4). Note that this mode uses the RxBound
indicator quite a bit differently from other modes, in that it
marks the start of each received block rather than the end.
Because of this, some of the mechanisms associated with
RxBound, that are described in later sections, aren’t of
much use in Nine-Bit mode. For example, you probably
wouldn’t want to store a Receive Status Block for an
address character.
The USC doesn’t use the MSBit of the RxSubMode field
(CMR7) in Nine Bit mode, but Zilog reserves this bit for
future enhancements, and software should program it as
0 in this mode.
UM009402-0201