Zilog Z16C30 User Manual

Page 62

4-13

Z16C30 USC

SER

ANUAL

ILOG

UM97USC0100

4.8 THE /DCD PIN

The

DCDMode

field of the I/O Control Register (IOCR13-

12) controls the function of this pin:

DCDMode

Function of the /DCD pin

Low-active Rx Carrier input

Low-active Rx Sync input

Low output

High output

When DCDMode is 00, software can handle the Carrier
indication all by itself. Or, the /DCD signal can enable and
disable the Receiver in hardware if software also programs
the RxEnable field of the Receive Mode Register (RMR1-
0) to 11. In the latter case, the Receiver starts assembling
a character only when /DCD is low; if /DCD goes high
during a received character, the Receiver aborts/discards
it. Figure 4-9 shows how the required relationship between
/DCD and RxD varies depends on the Receiver mode:

■

For isochronous mode, /DCD should set up low to the
rising edge of RxCLK at which the receiver samples
the start bit on RxD.

■

For monosync, bisync, and transparent bisync, /DCD
should set up low to the rising edge of RxCLK that
precedes the one at which the receiver samples the
first bit of the last sync pattern before the message.

■

For HDLC/SDLC mode, /DCD should set up low to the
rising edge of RxCLK at which the receiver samples
the ending 0 of the last Flag before the frame.

DCDMode=01 identifies the /DCD pin as an input from
external sync detection logic. Software typically programs
this value in conjunction with programming the RxMode
field of the Channel Mode Register (CMR3-0) with 0001 for
External Sync operation or 1001 for 802.3 (Ethernet) op-
eration. For External Sync mode, external logic should
drive the /DCD pin low so that it sets up to the rising edge
of RxCLK before the one at which the Receiver should
capture the first data bit. For 802.3 /DCD should go low
when carrier is detected — a figure in Chapter 5 shows that
the timing relationship to RxD isn’t critical but /DCD should
go low no later than 6 bits into the 64 alternating bits that
precede the frame. The Receiver starts sampling RxD at
the same rising edge of RxCLK at which it first samples
/DCD low. If /DCD goes high during a received character,
the Receiver completes receiving the character and trans-
fers it to the Receive FIFO before going inactive.

Sync conditions generated internal to the channel are not
output on this pin as on certain predecessor devices, but
can be output on the /RxC pin as described later.

The /DCD pin can alternatively be used as a general-
purpose output. To do this, simply program DCDMode to
10 to make the channel drive /DCD low, and to 11 to drive
the pin high. For such an application the designer may
want to connect a pull-up or pulldown resistor to the /DCD
pin, because the channel will not drive the pin from the time
/RESET goes low until the software programs DCDMode to
10 or 11.

UM009402-0201